initial commit

10 files changed, 771 insertions, 0 deletions

diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/analysis
new file mode 100644
index 0000000..7946c35
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/analysis
@@ -0,0 +1 @@
+.dc  v1 0e-00 5e-00 5e-03
diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9-cache.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9-cache.bak
new file mode 100644
index 0000000..ab4ac6a
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9-cache.bak
@@ -0,0 +1,109 @@
+EESchema-LIBRARY Version 2.3  Date: Monday 15 April 2013 09:47:58 PM IST
+#encoding utf-8
+#
+# dc
+#
+DEF dc v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "dc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# iplot
+#
+DEF iplot U 0 20 Y Y 1 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "iplot" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 -250 0 150 R 30 30 1 1 I
+X - 2 250 0 150 L 30 30 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PNP
+#
+DEF PNP Q 0 0 Y Y 1 F N
+F0 "Q" 0 -150 60 H V R CNN
+F1 "PNP" 0 150 60 H V R CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0  0 0  100 100 N
+P 3 0 1 10  0 75  0 -75  0 -75 F
+P 3 0 1 0  25 -25  0 0  0 0 N
+P 3 0 1 0  100 -100  65 -65  65 -65 N
+P 5 0 1 0  25 -25  50 -75  75 -50  25 -25  25 -25 F
+X E 1 100 -200 100 U 40 40 1 1 P
+X B 2 -200 0 200 R 40 40 1 1 I
+X C 3 100 200 100 D 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# vplot8_1
+#
+DEF vplot8_1 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8_1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+X + 2 0 -300 200 U 40 40 2 1 I
+X + 3 0 -300 200 U 40 40 3 1 I
+X + 4 0 -300 200 U 40 40 4 1 I
+X + 5 0 -300 200 U 40 40 5 1 I
+X + 6 0 -300 200 U 40 40 6 1 I
+X + 7 0 -300 200 U 40 40 7 1 I
+X + 8 0 -300 200 U 40 40 8 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9-cache.lib
new file mode 100644
index 0000000..19bc1ef
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9-cache.lib
@@ -0,0 +1,109 @@
+EESchema-LIBRARY Version 2.3  Date: Monday 13 May 2013 01:19:52 PM IST
+#encoding utf-8
+#
+# dc
+#
+DEF dc v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "dc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# iplot
+#
+DEF iplot U 0 20 Y Y 1 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "iplot" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 -250 0 150 R 30 30 1 1 I
+X - 2 250 0 150 L 30 30 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PNP
+#
+DEF PNP Q 0 0 Y Y 1 F N
+F0 "Q" 0 -150 60 H V R CNN
+F1 "PNP" 0 150 60 H V R CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0  0 0  100 100 N
+P 3 0 1 10  0 75  0 -75  0 -75 F
+P 3 0 1 0  25 -25  0 0  0 0 N
+P 3 0 1 0  100 -100  65 -65  65 -65 N
+P 5 0 1 0  25 -25  50 -75  75 -50  25 -25  25 -25 F
+X E 1 100 -200 100 U 40 40 1 1 P
+X B 2 -200 0 200 R 40 40 1 1 I
+X C 3 100 200 100 D 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# vplot8_1
+#
+DEF vplot8_1 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8_1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+X + 2 0 -300 200 U 40 40 2 1 I
+X + 3 0 -300 200 U 40 40 3 1 I
+X + 4 0 -300 200 U 40 40 4 1 I
+X + 5 0 -300 200 U 40 40 5 1 I
+X + 6 0 -300 200 U 40 40 6 1 I
+X + 7 0 -300 200 U 40 40 7 1 I
+X + 8 0 -300 200 U 40 40 8 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.bak
new file mode 100644
index 0000000..9b2890f
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.bak
@@ -0,0 +1,200 @@
+EESchema Schematic File Version 2  date Monday 15 April 2013 09:47:58 PM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+EELAYER 43  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "15 apr 2013"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Wire Line
+	4800 3600 4150 3600
+Wire Wire Line
+	6500 2900 6500 2050
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+Connection ~ 5100 2050
+Connection ~ 5100 2050
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 4750 3600
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+Connection ~ 4150 3600
+Connection ~ 3950 3600
+Connection ~ 4800 3600
+Connection ~ 3650 4850
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 516C1E89
+P 3650 4850
+F 0 "#FLG01" H 3650 5120 30  0001 C CNN
+F 1 "PWR_FLAG" H 3650 5080 30  0000 C CNN
+	1    3650 4850
+	1    0    0    -1  
+$EndComp
+$Comp
+L VPLOT8_1 U2
+U 1 1 516C1EFD
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+F 0 "U2" H 4600 3400 50  0000 C CNN
+F 1 "VPLOT8_1" H 4900 3400 50  0000 C CNN
+	1    4750 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 516C1E7B
+P 3650 5100
+F 0 "#PWR02" H 3650 5100 30  0001 C CNN
+F 1 "GND" H 3650 5030 30  0001 C CNN
+	1    3650 5100
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R1
+U 1 1 516C1E56
+P 3900 3600
+F 0 "R1" V 3980 3600 50  0000 C CNN
+F 1 "10000" V 3900 3600 50  0000 C CNN
+	1    3900 3600
+	0    1    1    0   
+$EndComp
+$Comp
+L VPLOT8_1 U2
+U 3 1 516C1E37
+P 5400 3900
+F 0 "U2" H 5250 4000 50  0000 C CNN
+F 1 "VPLOT8_1" H 5550 4000 50  0000 C CNN
+	3    5400 3900
+	0    1    1    0   
+$EndComp
+$Comp
+L R R3
+U 1 1 516C1E04
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+F 1 "10000" V 5100 4850 50  0000 C CNN
+	1    5100 4850
+	1    0    0    -1  
+$EndComp
+$Comp
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+U 1 1 516C1DF8
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+F 1 "IPLOT" H 5250 4300 50  0000 C CNN
+	1    5100 4200
+	0    1    1    0   
+$EndComp
+$Comp
+L VPLOT8_1 U2
+U 2 1 516C1DCB
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+F 1 "VPLOT8_1" H 5550 3450 50  0000 C CNN
+	2    5400 3350
+	0    1    1    0   
+$EndComp
+$Comp
+L DC v1
+U 1 1 516C1DBD
+P 6500 3350
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+F 1 "5" H 6300 3300 60  0000 C CNN
+F 2 "R1" H 6200 3350 60  0000 C CNN
+	1    6500 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L IPLOT U3
+U 1 1 516C1DAD
+P 5100 3000
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+F 1 "IPLOT" H 5250 3100 50  0000 C CNN
+	1    5100 3000
+	0    1    1    0   
+$EndComp
+$Comp
+L R R2
+U 1 1 516C1D7F
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+F 1 "1000" V 5100 2400 50  0000 C CNN
+	1    5100 2400
+	1    0    0    -1  
+$EndComp
+$Comp
+L PNP Q1
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+F 1 "PNP" H 5000 3750 60  0000 R CNN
+	1    5000 3600
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+$EndComp
+$EndSCHEMATC
diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir
new file mode 100644
index 0000000..484dfb8
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir
@@ -0,0 +1,17 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 13 May 2013 01:19:49 PM IST
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+v2  0 4 5		
+U2  2 6 3 VPLOT8_1		
+R1  2 0 10000		
+R3  5 4 10000		
+U4  3 5 IPLOT		
+v1  7 0 5		
+U3  8 6 IPLOT		
+R2  7 8 1000		
+Q1  3 2 6 PNP		
+
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir.ckt
new file mode 100644
index 0000000..3c4d3e8
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir.ckt
@@ -0,0 +1,17 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 01:19:49 pm ist
+
+v2  0 4 5
+* Plotting option vplot8_1
+r1  2 0 10000
+r3  5 4 10000
+V_u4 3 5 0
+v1  7 0 5
+V_u3 8 6 0
+r2  7 8 1000
+q1 6 2 3 pnp
+
+.dc  v1 0e-00 5e-00 5e-03
+.plot v(2) v(6) v(3) 
+.plot i(V_u4)
+.plot i(V_u3)
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir.out
new file mode 100644
index 0000000..00c3815
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir.out
@@ -0,0 +1,22 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 01:19:49 pm ist
+
+v2  0 4 5
+* Plotting option vplot8_1
+r1  2 0 10000
+r3  5 4 10000
+V_u4 3 5 0
+v1  7 0 5
+V_u3 8 6 0
+r2  7 8 1000
+q1 6 2 3 pnp
+
+.dc  v1 0e-00 5e-00 5e-03
+
+* Control Statements 
+.control
+run
+plot v(2) v(6) v(3) 
+plot i(V_u4)
+plot i(V_u3)
+.endc
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.pro
new file mode 100644
index 0000000..50bea06
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.pro
@@ -0,0 +1,74 @@
+update=Monday 15 April 2013 09:01:17 PM IST
+last_client=eeschema
+[eeschema]
+version=1
+LibDir=
+NetFmt=1
+HPGLSpd=20
+HPGLDm=15
+HPGLNum=1
+offX_A4=0
+offY_A4=0
+offX_A3=0
+offY_A3=0
+offX_A2=0
+offY_A2=0
+offX_A1=0
+offY_A1=0
+offX_A0=0
+offY_A0=0
+offX_A=0
+offY_A=0
+offX_B=0
+offY_B=0
+offX_C=0
+offY_C=0
+offX_D=0
+offY_D=0
+offX_E=0
+offY_E=0
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=/home/holy/OSCAD/library/analogSpice
+LibName32=/home/holy/OSCAD/library/analogXSpice
+LibName33=/home/holy/OSCAD/library/convergenceAidSpice
+LibName34=/home/holy/OSCAD/library/converterSpice
+LibName35=/home/holy/OSCAD/library/digitalSpice
+LibName36=/home/holy/OSCAD/library/digitalXSpice
+LibName37=/home/holy/OSCAD/library/linearSpice
+LibName38=/home/holy/OSCAD/library/measurementSpice
+LibName39=/home/holy/OSCAD/library/portSpice
+LibName40=/home/holy/OSCAD/library/sourcesSpice
diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.proj
new file mode 100644
index 0000000..cf438f1
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.proj
@@ -0,0 +1 @@
+schematicFile example_3.9.sch
diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.sch
new file mode 100644
index 0000000..da988b4
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.sch
@@ -0,0 +1,221 @@
+EESchema Schematic File Version 2  date Monday 13 May 2013 01:19:52 PM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:example_3.9-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "13 may 2013"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
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+$Comp
+L GND #PWR01
+U 1 1 51909AF0
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+F 0 "#PWR01" H 6700 3550 30  0001 C CNN
+F 1 "GND" H 6700 3480 30  0001 C CNN
+	1    6700 3550
+	1    0    0    -1  
+$EndComp
+Connection ~ 6500 3550
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+Wire Wire Line
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+Connection ~ 4750 3600
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+$Comp
+L DC v2
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