| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | analysis | 27 | logplain |
| -rw-r--r-- | example_3.7-cache.bak | 2001 | logplain |
| -rw-r--r-- | example_3.7-cache.lib | 2001 | logplain |
| -rw-r--r-- | example_3.7.bak | 3001 | logplain |
| -rw-r--r-- | example_3.7.cir | 438 | logplain |
| -rw-r--r-- | example_3.7.cir.ckt | 276 | logplain |
| -rw-r--r-- | example_3.7.cir.out | 315 | logplain |
| -rw-r--r-- | example_3.7.pro | 1409 | logplain |
| -rw-r--r-- | example_3.7.proj | 30 | logplain |
| -rw-r--r-- | example_3.7.sch | 3030 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |