| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | analysis | 26 | logplain |
| -rw-r--r-- | example_3.12-cache.bak | 2013 | logplain |
| -rw-r--r-- | example_3.12-cache.lib | 2010 | logplain |
| -rw-r--r-- | example_3.12.bak | 3683 | logplain |
| -rw-r--r-- | example_3.12.cir | 476 | logplain |
| -rw-r--r-- | example_3.12.cir.ckt | 290 | logplain |
| -rw-r--r-- | example_3.12.cir.out | 329 | logplain |
| -rw-r--r-- | example_3.12.pro | 1968 | logplain |
| -rw-r--r-- | example_3.12.proj | 31 | logplain |
| -rw-r--r-- | example_3.12.sch | 3963 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |