| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | analysis | 27 | logplain |
| -rw-r--r-- | example_2.8-cache.bak | 1706 | logplain |
| -rw-r--r-- | example_2.8-cache.lib | 1706 | logplain |
| -rw-r--r-- | example_2.8.bak | 2259 | logplain |
| -rw-r--r-- | example_2.8.cir | 403 | logplain |
| -rw-r--r-- | example_2.8.cir.ckt | 198 | logplain |
| -rw-r--r-- | example_2.8.cir.out | 239 | logplain |
| -rw-r--r-- | example_2.8.proj | 30 | logplain |
| -rw-r--r-- | example_2.8.sch | 2098 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |