| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | analysis | 26 | logplain |
| -rw-r--r-- | diode.lib | 184 | logplain |
| -rw-r--r-- | example_2.5-cache.bak | 1862 | logplain |
| -rw-r--r-- | example_2.5-cache.lib | 1862 | logplain |
| -rw-r--r-- | example_2.5.bak | 2879 | logplain |
| -rw-r--r-- | example_2.5.cir | 432 | logplain |
| -rw-r--r-- | example_2.5.cir.ckt | 277 | logplain |
| -rw-r--r-- | example_2.5.cir.out | 317 | logplain |
| -rw-r--r-- | example_2.5.pro | 1966 | logplain |
| -rw-r--r-- | example_2.5.proj | 30 | logplain |
| -rw-r--r-- | example_2.5.sch | 2967 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |