diff options
Diffstat (limited to 'OSCAD/Examples/sedra_smith/chapter_5')
154 files changed, 12141 insertions, 0 deletions
diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/analysis new file mode 100644 index 0000000..1665db7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 100e-03 100e-06 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.bak new file mode 100644 index 0000000..7a3e4b4 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.bak @@ -0,0 +1,126 @@ +EESchema-LIBRARY Version 2.3 Date: Thursday 09 May 2013 05:04:50 PM IST +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# LM741 +# +DEF LM741 U 0 20 Y Y 1 F N +F0 "U" 150 150 60 H V C CNN +F1 "LM741" 150 250 60 H V C CNN +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X ~ 1 0 -400 300 U 40 40 1 1 I +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X V- 4 -100 -400 250 U 40 40 1 1 I +X ~ 5 100 -400 350 U 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +X V+ 7 -100 400 250 D 40 40 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.lib new file mode 100644 index 0000000..5b4c901 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.lib @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 13 May 2013 10:18:21 AM IST +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.bak new file mode 100644 index 0000000..abf9a53 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.bak @@ -0,0 +1,181 @@ +EESchema Schematic File Version 2 date Thursday 09 May 2013 05:04:50 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "9 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L LM741 U? +U 1 1 518B89AE +P 8800 3550 +F 0 "U?" H 8950 3700 60 0000 C CNN +F 1 "LM741" H 8950 3800 60 0000 C CNN + 1 8800 3550 + 1 0 0 -1 +$EndComp +$Comp +L UA741 X? +U 1 1 518B899E +P 9050 2450 +F 0 "X?" H 9200 2600 60 0000 C CNN +F 1 "UA741" H 9200 2700 60 0000 C CNN + 1 9050 2450 + 1 0 0 -1 +$EndComp +$Comp +L SINE v1 +U 1 1 516F84E1 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "SINE" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7150 3300 6350 3300 +Wire Wire Line + 5300 2400 5300 3200 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 5350 4200 5350 3400 +Connection ~ 5300 3200 +Wire Wire Line + 5350 3200 5250 3200 +Wire Wire Line + 4150 3200 4050 3200 +Connection ~ 5350 4100 +Connection ~ 6350 3300 +Connection ~ 7050 3300 +Wire Wire Line + 5350 4100 4050 4100 +Wire Wire Line + 6900 2400 7050 2400 +Wire Wire Line + 7050 2400 7050 3300 +Wire Wire Line + 6400 2400 5800 2400 +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7050 3600 +F 0 "U3" H 6900 3700 50 0000 C CNN +F 1 "VPLOT8_1" H 7200 3700 50 0000 C CNN + 1 7050 3600 + -1 0 0 1 +$EndComp +$Comp +L PWR_FLAG #FLG1 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG1" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2400 +F 0 "U2" H 5400 2500 50 0000 C CNN +F 1 "IPLOT" H 5700 2500 50 0000 C CNN + 1 5550 2400 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6650 2400 +F 0 "R2" V 6730 2400 50 0000 C CNN +F 1 "10000" V 6650 2400 50 0000 C CNN + 1 6650 2400 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR1 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR1" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "1000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir new file mode 100644 index 0000000..d11b7e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir @@ -0,0 +1,24 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Thursday 18 April 2013 10:42:46 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +v1 4 0 PULSE +v2 11 0 10V +U3 8 3 VPLOT8_1 +R5 13 3 10000 +R4 0 13 10000 +R3 1 11 10000 +U5 8 2 IPLOT +Q2 1 1 2 NPN +X2 1 13 3 UA741 +U4 10 8 IPLOT +Q1 10 0 9 NPN +U1 6 7 IPLOT +U2 7 9 IPLOT +R2 8 5 10000 +R1 6 4 1000 +X1 7 0 5 UA741 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.ckt new file mode 100644 index 0000000..db0e45e --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.ckt @@ -0,0 +1,16 @@ +* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 02:25:09 pm ist +.include ua741.sub + +* Plotting option vplot8_1 +V_u1 6 5 0 +V_u2 5 4 0 +r2 1 4 100000 +v1 3 0 100m +r1 6 3 1000 +x1 5 0 1 ua741 + +.dc v1 0e-00 100e-03 100e-06 +.plot v(1) +.plot i(V_u1) +.plot i(V_u2) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.out new file mode 100644 index 0000000..d01be76 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.out @@ -0,0 +1,21 @@ +* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 02:25:09 pm ist +.include ua741.sub + +* Plotting option vplot8_1 +V_u1 6 5 0 +V_u2 5 4 0 +r2 1 4 100000 +v1 3 0 100m +r1 6 3 1000 +x1 5 0 1 ua741 + +.dc v1 0e-00 100e-03 100e-06 + +* Control Statements +.control +run +plot v(1) +plot i(V_u1) +plot i(V_u2) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.net b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.net new file mode 100644 index 0000000..6696e60 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.net @@ -0,0 +1,76 @@ +# EESchema Netlist Version 1.1 created Thursday 18 April 2013 11:00:24 AM IST +( + ( /516F84E1 R1 v1 SINE {Lib=SINE} + ( 1 N-000005 ) + ( 2 GND ) + ) + ( /516D117B $noname U3 VPLOT8_1 {Lib=VPLOT8_1} + ( 1 N-000004 ) + ) + ( /516D1019 $noname U1 IPLOT {Lib=IPLOT} + ( 1 N-000002 ) + ( 2 N-000003 ) + ) + ( /516D0FEC $noname U2 IPLOT {Lib=IPLOT} + ( 1 N-000003 ) + ( 2 N-000001 ) + ) + ( /516D0FE2 $noname R2 10000 {Lib=R} + ( 1 N-000004 ) + ( 2 N-000001 ) + ) + ( /516D0F10 $noname R1 1000 {Lib=R} + ( 1 N-000002 ) + ( 2 N-000005 ) + ) + ( /516D0E60 $noname X1 UA741 {Lib=UA741} + ( 2 N-000003 ) + ( 3 GND ) + ( 6 N-000004 ) + ) +) +* +{ Allowed footprints by component: +$component v1 + 1_pin +$endlist +$component R2 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R1 + R? + SM0603 + SM0805 + R?-* +$endlist +$component X1 + DIP-8__300 +$endlist +$endfootprintlist +} +{ Pin List by Nets +Net 1 "" "" + R2 2 + U2 2 +Net 2 "" "" + R1 1 + U1 1 +Net 3 "" "" + X1 2 + U2 1 + U1 2 +Net 4 "" "" + U3 1 + R2 1 + X1 6 +Net 5 "" "" + v1 1 + R1 2 +Net 6 "GND" "GND" + X1 3 + v1 2 +} +#End diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.pro new file mode 100644 index 0000000..2d33bde --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.pro @@ -0,0 +1,74 @@ +update=Tuesday 16 April 2013 02:06:21 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.proj new file mode 100644 index 0000000..fb6ad90 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.proj @@ -0,0 +1 @@ +schematicFile example_5.1.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.sch new file mode 100644 index 0000000..9267154 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.sch @@ -0,0 +1,163 @@ +EESchema Schematic File Version 2 date Monday 13 May 2013 10:18:21 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "13 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L SINE v1 +U 1 1 516F84E1 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "SINE" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7150 3300 6350 3300 +Wire Wire Line + 5300 2400 5300 3200 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 5350 4200 5350 3400 +Connection ~ 5300 3200 +Wire Wire Line + 5350 3200 5250 3200 +Wire Wire Line + 4150 3200 4050 3200 +Connection ~ 5350 4100 +Connection ~ 6350 3300 +Connection ~ 7050 3300 +Wire Wire Line + 5350 4100 4050 4100 +Wire Wire Line + 6900 2400 7050 2400 +Wire Wire Line + 7050 2400 7050 3300 +Wire Wire Line + 6400 2400 5800 2400 +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7050 3600 +F 0 "U3" H 6900 3700 50 0000 C CNN +F 1 "VPLOT8_1" H 7200 3700 50 0000 C CNN + 1 7050 3600 + -1 0 0 1 +$EndComp +$Comp +L PWR_FLAG #FLG1 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG1" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2400 +F 0 "U2" H 5400 2500 50 0000 C CNN +F 1 "IPLOT" H 5700 2500 50 0000 C CNN + 1 5550 2400 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6650 2400 +F 0 "R2" V 6730 2400 50 0000 C CNN +F 1 "10000" V 6650 2400 50 0000 C CNN + 1 6650 2400 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR1 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR1" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "1000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741-cache.lib new file mode 100644 index 0000000..e9ec641 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 16 April 2013 02:55:26 PM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.bak new file mode 100644 index 0000000..6be9280 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir new file mode 100644 index 0000000..de79742 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.ckt new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.out new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.out @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.pro new file mode 100644 index 0000000..46bdf8d --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.pro @@ -0,0 +1,82 @@ +update=Tuesday 16 April 2013 02:56:39 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice +LibName39=/home/holy/OSCAD/library/analogSpice +LibName40=/home/holy/OSCAD/library/analogXSpice +LibName41=/home/holy/OSCAD/library/convergenceAidSpice +LibName42=/home/holy/OSCAD/library/converterSpice +LibName43=/home/holy/OSCAD/library/digitalSpice +LibName44=/home/holy/OSCAD/library/digitalXSpice +LibName45=/home/holy/OSCAD/library/linearSpice +LibName46=/home/holy/OSCAD/library/measurementSpice +LibName47=/home/holy/OSCAD/library/portSpice +LibName48=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sch new file mode 100644 index 0000000..7dfc5e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sub new file mode 100644 index 0000000..1edba9f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sub @@ -0,0 +1,11 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 + +.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/analysis new file mode 100644 index 0000000..63f4a40 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/analysis @@ -0,0 +1,8 @@ + +.ac lin 20 1Hz 10Meg + + +.end +.control +run +.endc diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10-cache.bak new file mode 100644 index 0000000..3c7e9ce --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10-cache.bak @@ -0,0 +1,97 @@ +EESchema-LIBRARY Version 2.3 Date: Sunday 12 May 2013 08:39:09 PM IST +#encoding utf-8 +# +# AC +# +DEF AC AC 0 40 Y Y 1 F N +F0 "AC" -200 100 60 H V C CNN +F1 "AC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10-cache.lib new file mode 100644 index 0000000..1541b6a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10-cache.lib @@ -0,0 +1,97 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 13 May 2013 01:50:16 PM IST +#encoding utf-8 +# +# AC +# +DEF AC AC 0 40 Y Y 1 F N +F0 "AC" -200 100 60 H V C CNN +F1 "AC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.bak new file mode 100644 index 0000000..7d24c57 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.bak @@ -0,0 +1,143 @@ +EESchema Schematic File Version 2 date Sunday 12 May 2013 08:39:09 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.10-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "12 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 5200 3800 +$Comp +L VPLOT8_1 U1 +U 1 1 51877E04 +P 5200 4100 +F 0 "U1" H 5050 4200 50 0000 C CNN +F 1 "VPLOT8_1" H 5350 4200 50 0000 C CNN + 1 5200 4100 + -1 0 0 1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 2 1 51877DFD +P 6500 3400 +F 0 "U1" H 6350 3500 50 0000 C CNN +F 1 "VPLOT8_1" H 6650 3500 50 0000 C CNN + 2 6500 3400 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 51877DEF +P 4850 4700 +F 0 "#FLG01" H 4850 4970 30 0001 C CNN +F 1 "PWR_FLAG" H 4850 4930 30 0000 C CNN + 1 4850 4700 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 51877DE4 +P 4850 4850 +F 0 "#PWR02" H 4850 4850 30 0001 C CNN +F 1 "GND" H 4850 4780 30 0001 C CNN + 1 4850 4850 + 1 0 0 -1 +$EndComp +Connection ~ 4850 4700 +Wire Wire Line + 4850 4700 4850 4850 +Connection ~ 6350 3700 +Wire Wire Line + 6500 3700 6250 3700 +Wire Wire Line + 5050 3800 5250 3800 +Wire Wire Line + 5250 3600 5050 3600 +Wire Wire Line + 5150 3600 5150 3200 +Connection ~ 5150 3600 +Wire Wire Line + 5150 3200 6350 3200 +Wire Wire Line + 6350 3200 6350 3700 +Wire Wire Line + 4550 3600 4550 4700 +Wire Wire Line + 4550 4700 5050 4700 +$Comp +L AC V1 +U 1 1 51877DB5 +P 5050 4250 +F 0 "V1" H 4850 4350 60 0000 C CNN +F 1 "AC" H 4850 4200 60 0000 C CNN +F 2 "R1" H 4750 4250 60 0000 C CNN + 1 5050 4250 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 51877DA4 +P 4800 3600 +F 0 "R1" V 4880 3600 50 0000 C CNN +F 1 "R" V 4800 3600 50 0000 C CNN + 1 4800 3600 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 51877D93 +P 5750 3700 +F 0 "X1" H 5900 3850 60 0000 C CNN +F 1 "UA741" H 5900 3950 60 0000 C CNN + 1 5750 3700 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir new file mode 100644 index 0000000..103691f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir @@ -0,0 +1,13 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 13 May 2013 01:50:12 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +R2 1 4 100k +U1 3 1 VPLOT8_1 +V1 3 0 AC +R1 4 0 1k +X1 3 4 1 UA741 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir.ckt new file mode 100644 index 0000000..b3db0c4 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir.ckt @@ -0,0 +1,12 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 01:50:12 pm ist +.include ua741.sub + +r2 1 4 100k +* Plotting option vplot8_1 +v1 3 0 ac 1 +r1 4 0 1k +x1 3 4 1 ua741 + +.ac lin 10 1Hz 1Meg +.plot v(3) v(1) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir.out new file mode 100644 index 0000000..3554667 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir.out @@ -0,0 +1,17 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 01:50:12 pm ist +.include ua741.sub + +r2 1 4 100k +* Plotting option vplot8_1 +v1 3 0 ac 1 +r1 4 0 1k +x1 3 4 1 ua741 + +.ac lin 10 1Hz 1Meg + +* Control Statements +.control +run +plot v(3) v(1) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.pro new file mode 100644 index 0000000..77913bc --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.pro @@ -0,0 +1,74 @@ +update=Monday 06 May 2013 03:19:21 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice 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+LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.10-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "13 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 6000 3200 6350 3200 +Connection ~ 5200 3800 +Connection ~ 4850 4700 +Wire Wire Line + 4850 4700 4850 4850 +Connection ~ 6350 3700 +Wire Wire Line + 6500 3700 6250 3700 +Wire Wire Line + 5050 3800 5250 3800 +Wire Wire Line + 5250 3600 5050 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4850 4850 + 1 0 0 -1 +$EndComp +$Comp +L AC V1 +U 1 1 51877DB5 +P 5050 4250 +F 0 "V1" H 4850 4350 60 0000 C CNN +F 1 "AC" H 4850 4200 60 0000 C CNN +F 2 "R1" H 4750 4250 60 0000 C CNN + 1 5050 4250 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 51877DA4 +P 4800 3600 +F 0 "R1" V 4880 3600 50 0000 C CNN +F 1 "1k" V 4800 3600 50 0000 C CNN + 1 4800 3600 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 51877D93 +P 5750 3700 +F 0 "X1" H 5900 3850 60 0000 C CNN +F 1 "UA741" H 5900 3950 60 0000 C CNN + 1 5750 3700 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741-cache.bak new file mode 100644 index 0000000..696ddb5 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741-cache.bak @@ -0,0 +1,116 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 07 May 2013 04:32:37 PM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 0 -50 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCCS +# +DEF VCCS G 0 40 Y Y 1 F N +F0 "G" -200 100 50 H V C CNN +F1 "VCCS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741-cache.lib new file mode 100644 index 0000000..4ffd70b --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741-cache.lib @@ -0,0 +1,116 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 08 May 2013 02:27:06 PM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 0 -50 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCCS +# +DEF VCCS G 0 40 Y Y 1 F N +F0 "G" -200 100 50 H V C CNN +F1 "VCCS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.bak new file mode 100644 index 0000000..6be9280 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir new file mode 100644 index 0000000..de79742 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir.ckt new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir.out new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir.out @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.pro new file mode 100644 index 0000000..e55b2df --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.pro @@ -0,0 +1,82 @@ +update=Sunday 12 May 2013 08:34:27 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice +LibName39=/home/holy/OSCAD/library/analogSpice +LibName40=/home/holy/OSCAD/library/analogXSpice +LibName41=/home/holy/OSCAD/library/convergenceAidSpice +LibName42=/home/holy/OSCAD/library/converterSpice +LibName43=/home/holy/OSCAD/library/digitalSpice +LibName44=/home/holy/OSCAD/library/digitalXSpice +LibName45=/home/holy/OSCAD/library/linearSpice +LibName46=/home/holy/OSCAD/library/measurementSpice +LibName47=/home/holy/OSCAD/library/portSpice +LibName48=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.sch new file mode 100644 index 0000000..7dfc5e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.sub new file mode 100644 index 0000000..1edba9f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.sub @@ -0,0 +1,11 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 + +.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/analysis new file mode 100644 index 0000000..7946c35 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 5e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2-cache.lib new file mode 100644 index 0000000..40f51d7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 16 April 2013 03:05:48 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.bak new file mode 100644 index 0000000..9eb4b13 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.bak @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 date Tuesday 16 April 2013 02:59:48 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "16 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5350 4100 4050 4100 +Wire Wire Line + 6400 3350 6400 2950 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 5350 4200 5350 3400 +Connection ~ 5300 3200 +Wire Wire Line + 5300 2950 5300 3200 +Wire Wire Line + 5350 3200 5250 3200 +Connection ~ 6400 3300 +Wire Wire Line + 5900 2950 5800 2950 +Wire Wire Line + 4150 3200 4050 3200 +Connection ~ 5350 4100 +Wire Wire Line + 6350 3300 6400 3300 +Connection ~ 6350 3300 +Connection ~ 6400 3350 +$Comp +L PWR_FLAG #FLG01 +U 1 1 516D11A2 +P 5350 4100 +F 0 "#FLG01" H 5350 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN + 1 5350 4100 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 6700 3350 +F 0 "U3" H 6550 3450 50 0000 C CNN +F 1 "VPLOT8_1" H 6850 3450 50 0000 C CNN + 1 6700 3350 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG02" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2950 +F 0 "U2" H 5400 3050 50 0000 C CNN +F 1 "IPLOT" H 5700 3050 50 0000 C CNN + 1 5550 2950 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6150 2950 +F 0 "R2" V 6230 2950 50 0000 C CNN +F 1 "100000" V 6150 2950 50 0000 C CNN + 1 6150 2950 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 516D0FD3 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "100m" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR03" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "1000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir new file mode 100644 index 0000000..b0ee189 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir @@ -0,0 +1,19 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Tuesday 16 April 2013 03:05:45 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U5 3 8 IPLOT +U4 2 VPLOT8_1 +R3 0 2 100000 +R4 3 2 100000 +U3 8 VPLOT8_1 +U1 6 4 IPLOT +U2 4 5 IPLOT +R2 2 5 100000 +v1 7 0 100m +R1 6 7 1000 +X1 4 0 8 UA741 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir.ckt new file mode 100644 index 0000000..ea512f4 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir.ckt @@ -0,0 +1,22 @@ +* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 03:05:45 pm ist +.include ua741.sub + +V_u5 3 8 0 +* Plotting option vplot8_1 +r3 0 2 100000 +r4 3 2 100000 +* Plotting option vplot8_1 +V_u1 6 4 0 +V_u2 4 5 0 +r2 2 5 100000 +v1 7 0 100m +r1 6 7 1000 +x1 4 0 8 ua741 + +.dc v1 0e-00 5e-00 5e-03 +.plot i(V_u5) +.plot v(2) +.plot v(8) +.plot i(V_u1) +.plot i(V_u2) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir.out new file mode 100644 index 0000000..fdcc306 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir.out @@ -0,0 +1,27 @@ +* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 03:05:45 pm ist +.include ua741.sub + +V_u5 3 8 0 +* Plotting option vplot8_1 +r3 0 2 100000 +r4 3 2 100000 +* Plotting option vplot8_1 +V_u1 6 4 0 +V_u2 4 5 0 +r2 2 5 100000 +v1 7 0 100m +r1 6 7 1000 +x1 4 0 8 ua741 + +.dc v1 0e-00 5e-00 5e-03 + +* Control Statements +.control +run +plot i(V_u5) +plot v(2) +plot v(8) +plot i(V_u1) +plot i(V_u2) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.pro new file mode 100644 index 0000000..4197879 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.pro @@ -0,0 +1,74 @@ +update=Tuesday 16 April 2013 02:59:20 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.proj new file mode 100644 index 0000000..e56c1d2 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.proj @@ -0,0 +1 @@ +schematicFile example_5.2.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.sch new file mode 100644 index 0000000..5dbaecc --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.sch @@ -0,0 +1,224 @@ +EESchema Schematic File Version 2 date Tuesday 16 April 2013 03:05:48 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "16 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 7000 3000 7000 3350 +Connection ~ 7000 2400 +Connection ~ 6450 2500 +Connection ~ 6450 2400 +Wire Wire Line + 6350 3300 7000 3300 +Wire Wire Line + 6450 2900 6450 3000 +Connection ~ 7000 3350 +Connection ~ 6350 3300 +Connection ~ 5350 4100 +Wire Wire Line + 4150 3200 4050 3200 +Wire Wire Line + 5900 2400 5800 2400 +Connection ~ 7000 3300 +Wire Wire Line + 5350 3200 5250 3200 +Connection ~ 5300 3200 +Wire Wire Line + 5350 4200 5350 3400 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 5350 4100 4050 4100 +Wire Wire Line + 6400 2400 6500 2400 +Wire Wire Line + 5300 2400 5300 3200 +Wire Wire Line + 7000 2400 7000 2500 +$Comp +L IPLOT U5 +U 1 1 516D1AB3 +P 7000 2750 +F 0 "U5" H 6850 2850 50 0000 C CNN +F 1 "IPLOT" H 7150 2850 50 0000 C CNN + 1 7000 2750 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U4 +U 1 1 516D1A8F +P 6450 2100 +F 0 "U4" H 6300 2200 50 0000 C CNN +F 1 "VPLOT8_1" H 6600 2200 50 0000 C CNN + 1 6450 2100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 516D1A5C +P 6450 3000 +F 0 "#PWR01" H 6450 3000 30 0001 C CNN +F 1 "GND" H 6450 2930 30 0001 C CNN + 1 6450 3000 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 516D1A47 +P 6450 2650 +F 0 "R3" V 6530 2650 50 0000 C CNN +F 1 "100000" V 6450 2650 50 0000 C CNN + 1 6450 2650 + -1 0 0 1 +$EndComp +$Comp +L R R4 +U 1 1 516D1A3E +P 6750 2400 +F 0 "R4" V 6830 2400 50 0000 C CNN +F 1 "100000" V 6750 2400 50 0000 C CNN + 1 6750 2400 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516D11A2 +P 5350 4100 +F 0 "#FLG02" H 5350 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN + 1 5350 4100 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7300 3350 +F 0 "U3" H 7150 3450 50 0000 C CNN +F 1 "VPLOT8_1" H 7450 3450 50 0000 C CNN + 1 7300 3350 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG03 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG03" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2400 +F 0 "U2" H 5400 2500 50 0000 C CNN +F 1 "IPLOT" H 5700 2500 50 0000 C CNN + 1 5550 2400 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6150 2400 +F 0 "R2" V 6230 2400 50 0000 C CNN +F 1 "100000" V 6150 2400 50 0000 C CNN + 1 6150 2400 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 516D0FD3 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "100m" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR04" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "1000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.bak new file mode 100644 index 0000000..6be9280 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir new file mode 100644 index 0000000..de79742 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir.ckt new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir.out new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir.out @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.pro new file mode 100644 index 0000000..34303c7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.pro @@ -0,0 +1,82 @@ +update=Tuesday 16 April 2013 03:06:44 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice +LibName39=/home/holy/OSCAD/library/analogSpice +LibName40=/home/holy/OSCAD/library/analogXSpice +LibName41=/home/holy/OSCAD/library/convergenceAidSpice +LibName42=/home/holy/OSCAD/library/converterSpice +LibName43=/home/holy/OSCAD/library/digitalSpice +LibName44=/home/holy/OSCAD/library/digitalXSpice +LibName45=/home/holy/OSCAD/library/linearSpice +LibName46=/home/holy/OSCAD/library/measurementSpice +LibName47=/home/holy/OSCAD/library/portSpice +LibName48=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.sch new file mode 100644 index 0000000..7dfc5e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.sub new file mode 100644 index 0000000..1edba9f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.sub @@ -0,0 +1,11 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 + +.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/analysis new file mode 100644 index 0000000..7946c35 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 5e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3-cache.bak new file mode 100644 index 0000000..e6f6afe --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3-cache.bak @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 15 May 2013 09:35:11 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3-cache.lib new file mode 100644 index 0000000..4daeb80 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 21 May 2013 11:13:50 AM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.bak new file mode 100644 index 0000000..d0ef6de --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.bak @@ -0,0 +1,182 @@ +EESchema Schematic File Version 2 date Wednesday 15 May 2013 09:35:11 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 7050 3300 7050 2950 +Wire Wire Line + 6450 3300 6350 3300 +Wire Wire Line + 5350 4100 4050 4100 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 5350 3400 5350 4200 +Connection ~ 5300 3200 +Wire Wire Line + 5300 2950 5300 3200 +Wire Wire Line + 5250 3200 5350 3200 +Wire Wire Line + 5900 2950 5800 2950 +Wire Wire Line + 4150 3200 4050 3200 +Connection ~ 5350 4100 +Connection ~ 6350 3300 +Connection ~ 7050 3300 +Wire Wire Line + 7050 3300 6950 3300 +Wire Wire Line + 7050 2950 6400 2950 +$Comp +L R R3 +U 1 1 516D1D5E +P 6700 3300 +F 0 "R3" V 6780 3300 50 0000 C CNN +F 1 "100k" V 6700 3300 50 0000 C CNN + 1 6700 3300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 516D11A2 +P 5350 4100 +F 0 "#FLG01" H 5350 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN + 1 5350 4100 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7350 3300 +F 0 "U3" H 7200 3400 50 0000 C CNN +F 1 "VPLOT8_1" H 7500 3400 50 0000 C CNN + 1 7350 3300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG02" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2950 +F 0 "U2" H 5400 3050 50 0000 C CNN +F 1 "IPLOT" H 5700 3050 50 0000 C CNN + 1 5550 2950 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6150 2950 +F 0 "R2" V 6230 2950 50 0000 C CNN +F 1 "1000" V 6150 2950 50 0000 C CNN + 1 6150 2950 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 516D0FD3 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "10" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR03" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "10" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir new file mode 100644 index 0000000..25f7e67 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir @@ -0,0 +1,16 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wednesday 15 May 2013 09:29:30 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +R3 1 7 100k +U3 1 VPLOT8_1 +U1 5 2 IPLOT +U2 2 3 IPLOT +R2 1 3 1000 +v1 6 0 10 +R1 5 6 10 +X1 2 0 7 UA741 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir.ckt new file mode 100644 index 0000000..5cc8d66 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir.ckt @@ -0,0 +1,17 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 15 may 2013 09:29:30 pm ist +.include ua741.sub + +r3 1 7 100k +* Plotting option vplot8_1 +V_u1 5 2 0 +V_u2 2 3 0 +r2 1 3 1000 +v1 6 0 10 +r1 5 6 10 +x1 2 0 7 ua741 + +.dc v1 0e-00 5e-00 5e-03 +.plot v(1) +.plot i(V_u1) +.plot i(V_u2) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir.out new file mode 100644 index 0000000..1d3b745 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir.out @@ -0,0 +1,22 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 15 may 2013 09:29:30 pm ist +.include ua741.sub + +r3 1 7 100k +* Plotting option vplot8_1 +V_u1 5 2 0 +V_u2 2 3 0 +r2 1 3 1000 +v1 6 0 10 +r1 5 6 10 +x1 2 0 7 ua741 + +.dc v1 0e-00 5e-00 5e-03 + +* Control Statements +.control +run +plot v(1) +plot i(V_u1) +plot i(V_u2) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.pro new file mode 100644 index 0000000..68ef472 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.pro @@ -0,0 +1,74 @@ +update=Tuesday 16 April 2013 03:20:48 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.proj new file mode 100644 index 0000000..36f23a8 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.proj @@ -0,0 +1 @@ +schematicFile example_5.3.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.sch new file mode 100644 index 0000000..a549a57 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.sch @@ -0,0 +1,183 @@ +EESchema Schematic File Version 2 date Tuesday 21 May 2013 11:13:50 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.3-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "21 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 7050 3300 7050 2950 +Wire Wire Line + 6450 3300 6350 3300 +Wire Wire Line + 5350 4100 4050 4100 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 5350 3400 5350 4200 +Connection ~ 5300 3200 +Wire Wire Line + 5300 2950 5300 3200 +Wire Wire Line + 5250 3200 5350 3200 +Wire Wire Line + 5900 2950 5800 2950 +Wire Wire Line + 4150 3200 4050 3200 +Connection ~ 5350 4100 +Connection ~ 6350 3300 +Connection ~ 7050 3300 +Wire Wire Line + 7050 3300 6950 3300 +Wire Wire Line + 7050 2950 6400 2950 +$Comp +L R RL +U 1 1 516D1D5E +P 6700 3300 +F 0 "RL" V 6780 3300 50 0000 C CNN +F 1 "100k" V 6700 3300 50 0000 C CNN + 1 6700 3300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 516D11A2 +P 5350 4100 +F 0 "#FLG01" H 5350 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN + 1 5350 4100 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7350 3300 +F 0 "U3" H 7200 3400 50 0000 C CNN +F 1 "VPLOT8_1" H 7500 3400 50 0000 C CNN + 1 7350 3300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG02" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2950 +F 0 "U2" H 5400 3050 50 0000 C CNN +F 1 "IPLOT" H 5700 3050 50 0000 C CNN + 1 5550 2950 + 1 0 0 -1 +$EndComp +$Comp +L R Rf +U 1 1 516D0FE2 +P 6150 2950 +F 0 "Rf" V 6230 2950 50 0000 C CNN +F 1 "1000" V 6150 2950 50 0000 C CNN + 1 6150 2950 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 516D0FD3 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "10" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR03" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "10" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.bak new file mode 100644 index 0000000..6be9280 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir new file mode 100644 index 0000000..de79742 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir.ckt new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir.out new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir.out @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.pro new file mode 100644 index 0000000..1f35813 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.pro @@ -0,0 +1,82 @@ +update=Wednesday 15 May 2013 09:42:35 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice +LibName39=/home/holy/OSCAD/library/analogSpice +LibName40=/home/holy/OSCAD/library/analogXSpice +LibName41=/home/holy/OSCAD/library/convergenceAidSpice +LibName42=/home/holy/OSCAD/library/converterSpice +LibName43=/home/holy/OSCAD/library/digitalSpice +LibName44=/home/holy/OSCAD/library/digitalXSpice +LibName45=/home/holy/OSCAD/library/linearSpice +LibName46=/home/holy/OSCAD/library/measurementSpice +LibName47=/home/holy/OSCAD/library/portSpice +LibName48=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.sch new file mode 100644 index 0000000..7dfc5e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.sub new file mode 100644 index 0000000..1edba9f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.sub @@ -0,0 +1,11 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 + +.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/analysis new file mode 100644 index 0000000..35318bb --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 10e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4-cache.bak new file mode 100644 index 0000000..c4ca8fc --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4-cache.bak @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 17 April 2013 12:43:16 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4-cache.lib new file mode 100644 index 0000000..18a7cf4 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 17 April 2013 12:47:25 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.bak new file mode 100644 index 0000000..f68a6c8 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.bak @@ -0,0 +1,345 @@ +EESchema Schematic File Version 2 date Wednesday 17 April 2013 12:43:16 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.4-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 1400 6300 +$Comp +L PWR_FLAG #FLG01 +U 1 1 516D2826 +P 1400 6300 +F 0 "#FLG01" H 1400 6570 30 0001 C CNN +F 1 "PWR_FLAG" H 1400 6530 30 0000 C CNN + 1 1400 6300 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 516D27F8 +P 1400 6450 +F 0 "#PWR02" H 1400 6450 30 0001 C CNN +F 1 "GND" H 1400 6380 30 0001 C CNN + 1 1400 6450 + 1 0 0 -1 +$EndComp +Connection ~ 1400 6100 +Wire Wire Line + 1400 6100 1400 6450 +Connection ~ 2400 3250 +Connection ~ 4500 3450 +Connection ~ 4500 4400 +Connection ~ 6750 3900 +Wire Wire Line + 5100 4700 5100 4850 +Wire Wire Line + 1600 5200 1600 5000 +Wire Wire Line + 1600 5000 2400 5000 +Connection ~ 3650 4900 +Wire Wire Line + 3900 4400 3900 4900 +Wire Wire Line + 3900 4900 3400 4900 +Connection ~ 2400 4500 +Wire Wire Line + 2400 4500 2600 4500 +Wire Wire Line + 3650 3000 3650 3550 +Wire Wire Line + 3650 3550 3100 3550 +Wire Wire Line + 2400 4250 2400 4800 +Wire Wire Line + 6750 3900 6750 3950 +Wire Wire Line + 6750 3950 6150 3950 +Wire Wire Line + 5300 3350 5100 3350 +Connection ~ 5100 3850 +Wire Wire Line + 5100 3350 5100 3850 +Wire Wire Line + 4400 3450 4550 3450 +Wire Wire Line + 4550 3450 4550 3850 +Wire Wire Line + 5150 3850 5050 3850 +Wire Wire Line + 5150 4050 5050 4050 +Wire Wire Line + 4550 4050 4550 4400 +Wire Wire Line + 4550 4400 4400 4400 +Wire Wire Line + 5800 3350 5950 3350 +Wire Wire Line + 6450 3350 6450 3950 +Connection ~ 6450 3950 +Wire Wire Line + 2400 3750 2400 3100 +Wire Wire Line + 2400 3550 2600 3550 +Connection ~ 2400 3550 +Wire Wire Line + 3400 3000 3900 3000 +Wire Wire Line + 3900 3000 3900 3450 +Connection ~ 3650 3000 +Wire Wire Line + 3100 4500 3650 4500 +Wire Wire Line + 3650 4500 3650 4900 +Wire Wire Line + 2400 2900 1150 2900 +Wire Wire Line + 1150 2900 1150 3600 +Wire Wire Line + 5100 4050 5100 4200 +Connection ~ 5100 4050 +Wire Wire Line + 1150 4500 1150 6100 +Wire Wire Line + 1150 6100 1600 6100 +$Comp +L DC v2 +U 1 1 516D27D5 +P 1600 5650 +F 0 "v2" H 1400 5750 60 0000 C CNN +F 1 "DC" H 1400 5600 60 0000 C CNN +F 2 "R1" H 1300 5650 60 0000 C CNN + 1 1600 5650 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 516D27D0 +P 1150 4050 +F 0 "v1" H 950 4150 60 0000 C CNN +F 1 "DC" H 950 4000 60 0000 C CNN +F 2 "R1" H 850 4050 60 0000 C CNN + 1 1150 4050 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 2 1 516D27AE +P 2400 4200 +F 0 "U1" H 2250 4300 50 0000 C CNN +F 1 "VPLOT8_1" H 2550 4300 50 0000 C CNN + 2 2400 4200 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 516D27A5 +P 2400 3250 +F 0 "U1" H 2250 3350 50 0000 C CNN +F 1 "VPLOT8_1" H 2550 3350 50 0000 C CNN + 1 2400 3250 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 5 1 516D278E +P 6750 3600 +F 0 "U1" H 6600 3700 50 0000 C CNN +F 1 "VPLOT8_1" H 6900 3700 50 0000 C CNN + 5 6750 3600 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 4 1 516D2789 +P 4500 4100 +F 0 "U1" H 4350 4200 50 0000 C CNN +F 1 "VPLOT8_1" H 4650 4200 50 0000 C CNN + 4 4500 4100 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 3 1 516D2785 +P 4500 3150 +F 0 "U1" H 4350 3250 50 0000 C CNN +F 1 "VPLOT8_1" H 4650 3250 50 0000 C CNN + 3 4500 3150 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516D274C +P 5100 4850 +F 0 "#PWR03" H 5100 4850 30 0001 C CNN +F 1 "GND" H 5100 4780 30 0001 C CNN + 1 5100 4850 + 1 0 0 -1 +$EndComp +$Comp +L R R6 +U 1 1 516D2736 +P 5100 4450 +F 0 "R6" V 5180 4450 50 0000 C CNN +F 1 "R" V 5100 4450 50 0000 C CNN + 1 5100 4450 + -1 0 0 1 +$EndComp +$Comp +L R R3 +U 1 1 516D26F4 +P 2850 4500 +F 0 "R3" V 2930 4500 50 0000 C CNN +F 1 "R" V 2850 4500 50 0000 C CNN + 1 2850 4500 + 0 -1 -1 0 +$EndComp +$Comp +L R R2 +U 1 1 516D26CE +P 2850 3550 +F 0 "R2" V 2930 3550 50 0000 C CNN +F 1 "R" V 2850 3550 50 0000 C CNN + 1 2850 3550 + 0 -1 -1 0 +$EndComp +$Comp +L R R1 +U 1 1 516D26AE +P 2400 4000 +F 0 "R1" V 2480 4000 50 0000 C CNN +F 1 "R" V 2400 4000 50 0000 C CNN + 1 2400 4000 + -1 0 0 1 +$EndComp +$Comp +L R R7 +U 1 1 516D268C +P 6200 3350 +F 0 "R7" V 6280 3350 50 0000 C CNN +F 1 "R" V 6200 3350 50 0000 C CNN + 1 6200 3350 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516D267F +P 5550 3350 +F 0 "U4" H 5400 3450 50 0000 C CNN +F 1 "IPLOT" H 5700 3450 50 0000 C CNN + 1 5550 3350 + 1 0 0 -1 +$EndComp +$Comp +L UA741 X2 +U 1 1 516D2661 +P 2900 4900 +F 0 "X2" H 3050 5050 60 0000 C CNN +F 1 "UA741" H 3050 5150 60 0000 C CNN + 1 2900 4900 + 1 0 0 1 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D2656 +P 2900 3000 +F 0 "X1" H 3050 3150 60 0000 C CNN +F 1 "UA741" H 3050 3250 60 0000 C CNN + 1 2900 3000 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U3 +U 1 1 516D264E +P 4150 4400 +F 0 "U3" H 4000 4500 50 0000 C CNN +F 1 "IPLOT" H 4300 4500 50 0000 C CNN + 1 4150 4400 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D2648 +P 4150 3450 +F 0 "U2" H 4000 3550 50 0000 C CNN +F 1 "IPLOT" H 4300 3550 50 0000 C CNN + 1 4150 3450 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 516D2600 +P 4800 4050 +F 0 "R5" V 4880 4050 50 0000 C CNN +F 1 "R" V 4800 4050 50 0000 C CNN + 1 4800 4050 + 0 1 1 0 +$EndComp +$Comp +L R R4 +U 1 1 516D25EC +P 4800 3850 +F 0 "R4" V 4880 3850 50 0000 C CNN +F 1 "R" V 4800 3850 50 0000 C CNN + 1 4800 3850 + 0 1 1 0 +$EndComp +$Comp +L UA741 X3 +U 1 1 516D25CD +P 5650 3950 +F 0 "X3" H 5800 4100 60 0000 C CNN +F 1 "UA741" H 5800 4200 60 0000 C CNN + 1 5650 3950 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir new file mode 100644 index 0000000..4788ef3 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir @@ -0,0 +1,24 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wednesday 17 April 2013 12:47:21 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +v2 5 0 10V +v1 9 0 20V +U1 3 4 6 2 11 VPLOT8_1 +R6 0 7 R +R3 4 12 R +R2 3 8 R +R1 4 3 R +R7 11 10 R +U4 13 10 IPLOT +X2 4 5 12 UA741 +X1 3 9 8 UA741 +U3 12 2 IPLOT +U2 8 6 IPLOT +R5 7 2 R +R4 13 6 R +X3 13 7 11 UA741 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir.ckt new file mode 100644 index 0000000..2fc3967 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir.ckt @@ -0,0 +1,26 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 17 april 2013 12:47:21 pm ist +.include ua741.sub + +v2 5 0 10v +v1 9 0 20v +* Plotting option vplot8_1 +r6 0 7 r +r3 4 12 r +r2 3 8 r +r1 4 3 r +r7 11 10 r +V_u4 13 10 0 +x2 4 5 12 ua741 +x1 3 9 8 ua741 +V_u3 12 2 0 +V_u2 8 6 0 +r5 7 2 r +r4 13 6 r +x3 13 7 11 ua741 + +.dc v1 0e-00 10e-00 5e-03 +.plot v(3) v(4) v(6) v(2) v(11) +.plot i(V_u4) +.plot i(V_u3) +.plot i(V_u2) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir.out new file mode 100644 index 0000000..98912a5 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir.out @@ -0,0 +1,31 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 17 april 2013 12:47:21 pm ist +.include ua741.sub + +v2 5 0 10v +v1 9 0 20v +* Plotting option vplot8_1 +r6 0 7 r +r3 4 12 r +r2 3 8 r +r1 4 3 r +r7 11 10 r +V_u4 13 10 0 +x2 4 5 12 ua741 +x1 3 9 8 ua741 +V_u3 12 2 0 +V_u2 8 6 0 +r5 7 2 r +r4 13 6 r +x3 13 7 11 ua741 + +.dc v1 0e-00 10e-00 5e-03 + +* Control Statements +.control +run +plot v(3) v(4) v(6) v(2) v(11) +plot i(V_u4) +plot i(V_u3) +plot i(V_u2) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.pro new file mode 100644 index 0000000..ac34f0e --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.pro @@ -0,0 +1,74 @@ +update=Tuesday 16 April 2013 03:49:31 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.proj new file mode 100644 index 0000000..799253b --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.proj @@ -0,0 +1 @@ +schematicFile example_5.4.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.sch new file mode 100644 index 0000000..8b83c0d --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.sch @@ -0,0 +1,345 @@ +EESchema Schematic File Version 2 date Wednesday 17 April 2013 12:47:25 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.4-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 1400 6300 +$Comp +L PWR_FLAG #FLG01 +U 1 1 516D2826 +P 1400 6300 +F 0 "#FLG01" H 1400 6570 30 0001 C CNN +F 1 "PWR_FLAG" H 1400 6530 30 0000 C CNN + 1 1400 6300 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 516D27F8 +P 1400 6450 +F 0 "#PWR02" H 1400 6450 30 0001 C CNN +F 1 "GND" H 1400 6380 30 0001 C CNN + 1 1400 6450 + 1 0 0 -1 +$EndComp +Connection ~ 1400 6100 +Wire Wire Line + 1400 6100 1400 6450 +Connection ~ 2400 3250 +Connection ~ 4500 3450 +Connection ~ 4500 4400 +Connection ~ 6750 3900 +Wire Wire Line + 5100 4700 5100 4850 +Wire Wire Line + 1600 5200 1600 5000 +Wire Wire Line + 1600 5000 2400 5000 +Connection ~ 3650 4900 +Wire Wire Line + 3900 4400 3900 4900 +Wire Wire Line + 3900 4900 3400 4900 +Connection ~ 2400 4500 +Wire Wire Line + 2400 4500 2600 4500 +Wire Wire Line + 3650 3000 3650 3550 +Wire Wire Line + 3650 3550 3100 3550 +Wire Wire Line + 2400 4250 2400 4800 +Wire Wire Line + 6750 3900 6750 3950 +Wire Wire Line + 6750 3950 6150 3950 +Wire Wire Line + 5300 3350 5100 3350 +Connection ~ 5100 3850 +Wire Wire Line + 5100 3350 5100 3850 +Wire Wire Line + 4400 3450 4550 3450 +Wire Wire Line + 4550 3450 4550 3850 +Wire Wire Line + 5150 3850 5050 3850 +Wire Wire Line + 5150 4050 5050 4050 +Wire Wire Line + 4550 4050 4550 4400 +Wire Wire Line + 4550 4400 4400 4400 +Wire Wire Line + 5800 3350 5950 3350 +Wire Wire Line + 6450 3350 6450 3950 +Connection ~ 6450 3950 +Wire Wire Line + 2400 3750 2400 3100 +Wire Wire Line + 2400 3550 2600 3550 +Connection ~ 2400 3550 +Wire Wire Line + 3400 3000 3900 3000 +Wire Wire Line + 3900 3000 3900 3450 +Connection ~ 3650 3000 +Wire Wire Line + 3100 4500 3650 4500 +Wire Wire Line + 3650 4500 3650 4900 +Wire Wire Line + 2400 2900 1150 2900 +Wire Wire Line + 1150 2900 1150 3600 +Wire Wire Line + 5100 4050 5100 4200 +Connection ~ 5100 4050 +Wire Wire Line + 1150 4500 1150 6100 +Wire Wire Line + 1150 6100 1600 6100 +$Comp +L DC v2 +U 1 1 516D27D5 +P 1600 5650 +F 0 "v2" H 1400 5750 60 0000 C CNN +F 1 "10V" H 1400 5600 60 0000 C CNN +F 2 "R1" H 1300 5650 60 0000 C CNN + 1 1600 5650 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 516D27D0 +P 1150 4050 +F 0 "v1" H 950 4150 60 0000 C CNN +F 1 "20V" H 950 4000 60 0000 C CNN +F 2 "R1" H 850 4050 60 0000 C CNN + 1 1150 4050 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 2 1 516D27AE +P 2400 4200 +F 0 "U1" H 2250 4300 50 0000 C CNN +F 1 "VPLOT8_1" H 2550 4300 50 0000 C CNN + 2 2400 4200 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 516D27A5 +P 2400 3250 +F 0 "U1" H 2250 3350 50 0000 C CNN +F 1 "VPLOT8_1" H 2550 3350 50 0000 C CNN + 1 2400 3250 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 5 1 516D278E +P 6750 3600 +F 0 "U1" H 6600 3700 50 0000 C CNN +F 1 "VPLOT8_1" H 6900 3700 50 0000 C CNN + 5 6750 3600 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 4 1 516D2789 +P 4500 4100 +F 0 "U1" H 4350 4200 50 0000 C CNN +F 1 "VPLOT8_1" H 4650 4200 50 0000 C CNN + 4 4500 4100 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 3 1 516D2785 +P 4500 3150 +F 0 "U1" H 4350 3250 50 0000 C CNN +F 1 "VPLOT8_1" H 4650 3250 50 0000 C CNN + 3 4500 3150 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516D274C +P 5100 4850 +F 0 "#PWR03" H 5100 4850 30 0001 C CNN +F 1 "GND" H 5100 4780 30 0001 C CNN + 1 5100 4850 + 1 0 0 -1 +$EndComp +$Comp +L R R6 +U 1 1 516D2736 +P 5100 4450 +F 0 "R6" V 5180 4450 50 0000 C CNN +F 1 "R" V 5100 4450 50 0000 C CNN + 1 5100 4450 + -1 0 0 1 +$EndComp +$Comp +L R R3 +U 1 1 516D26F4 +P 2850 4500 +F 0 "R3" V 2930 4500 50 0000 C CNN +F 1 "R" V 2850 4500 50 0000 C CNN + 1 2850 4500 + 0 -1 -1 0 +$EndComp +$Comp +L R R2 +U 1 1 516D26CE +P 2850 3550 +F 0 "R2" V 2930 3550 50 0000 C CNN +F 1 "R" V 2850 3550 50 0000 C CNN + 1 2850 3550 + 0 -1 -1 0 +$EndComp +$Comp +L R R1 +U 1 1 516D26AE +P 2400 4000 +F 0 "R1" V 2480 4000 50 0000 C CNN +F 1 "R" V 2400 4000 50 0000 C CNN + 1 2400 4000 + -1 0 0 1 +$EndComp +$Comp +L R R7 +U 1 1 516D268C +P 6200 3350 +F 0 "R7" V 6280 3350 50 0000 C CNN +F 1 "R" V 6200 3350 50 0000 C CNN + 1 6200 3350 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516D267F +P 5550 3350 +F 0 "U4" H 5400 3450 50 0000 C CNN +F 1 "IPLOT" H 5700 3450 50 0000 C CNN + 1 5550 3350 + 1 0 0 -1 +$EndComp +$Comp +L UA741 X2 +U 1 1 516D2661 +P 2900 4900 +F 0 "X2" H 3050 5050 60 0000 C CNN +F 1 "UA741" H 3050 5150 60 0000 C CNN + 1 2900 4900 + 1 0 0 1 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D2656 +P 2900 3000 +F 0 "X1" H 3050 3150 60 0000 C CNN +F 1 "UA741" H 3050 3250 60 0000 C CNN + 1 2900 3000 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U3 +U 1 1 516D264E +P 4150 4400 +F 0 "U3" H 4000 4500 50 0000 C CNN +F 1 "IPLOT" H 4300 4500 50 0000 C CNN + 1 4150 4400 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D2648 +P 4150 3450 +F 0 "U2" H 4000 3550 50 0000 C CNN +F 1 "IPLOT" H 4300 3550 50 0000 C CNN + 1 4150 3450 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 516D2600 +P 4800 4050 +F 0 "R5" V 4880 4050 50 0000 C CNN +F 1 "R" V 4800 4050 50 0000 C CNN + 1 4800 4050 + 0 1 1 0 +$EndComp +$Comp +L R R4 +U 1 1 516D25EC +P 4800 3850 +F 0 "R4" V 4880 3850 50 0000 C CNN +F 1 "R" V 4800 3850 50 0000 C CNN + 1 4800 3850 + 0 1 1 0 +$EndComp +$Comp +L UA741 X3 +U 1 1 516D25CD +P 5650 3950 +F 0 "X3" H 5800 4100 60 0000 C CNN +F 1 "UA741" H 5800 4200 60 0000 C CNN + 1 5650 3950 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.bak new file mode 100644 index 0000000..6be9280 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir new file mode 100644 index 0000000..de79742 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir.ckt new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir.out new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir.out @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.pro new file mode 100644 index 0000000..0d94955 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.pro @@ -0,0 +1,82 @@ +update=Wednesday 17 April 2013 12:46:01 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice +LibName39=/home/holy/OSCAD/library/analogSpice +LibName40=/home/holy/OSCAD/library/analogXSpice +LibName41=/home/holy/OSCAD/library/convergenceAidSpice +LibName42=/home/holy/OSCAD/library/converterSpice +LibName43=/home/holy/OSCAD/library/digitalSpice +LibName44=/home/holy/OSCAD/library/digitalXSpice +LibName45=/home/holy/OSCAD/library/linearSpice +LibName46=/home/holy/OSCAD/library/measurementSpice +LibName47=/home/holy/OSCAD/library/portSpice +LibName48=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.sch new file mode 100644 index 0000000..7dfc5e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.sub new file mode 100644 index 0000000..1edba9f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.sub @@ -0,0 +1,11 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 + +.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/analysis new file mode 100644 index 0000000..c9183fa --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/analysis @@ -0,0 +1 @@ +.tran 10e-03 20e-03 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.bak new file mode 100644 index 0000000..79f0251 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.bak @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 17 April 2013 11:57:44 AM IST +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.lib new file mode 100644 index 0000000..951b224 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.lib @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 17 April 2013 12:50:53 PM IST +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.bak new file mode 100644 index 0000000..9eaa078 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.bak @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 date Wednesday 17 April 2013 11:57:44 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L SINE v1 +U 1 1 516E3BC9 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "SINE" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 4100 4050 4100 +Wire Wire Line + 6350 3300 7050 3300 +Wire Wire Line + 6400 2950 7050 2950 +Connection ~ 7050 3300 +Connection ~ 6350 3300 +Connection ~ 5350 4100 +Wire Wire Line + 4150 3200 4050 3200 +Wire Wire Line + 5900 2950 5800 2950 +Wire Wire Line + 5350 3200 5250 3200 +Wire Wire Line + 5300 2950 5300 3200 +Connection ~ 5300 3200 +Wire Wire Line + 5350 4200 5350 3400 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 7050 2950 7050 3300 +$Comp +L PWR_FLAG #FLG01 +U 1 1 516D11A2 +P 5350 4100 +F 0 "#FLG01" H 5350 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN + 1 5350 4100 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7350 3300 +F 0 "U3" H 7200 3400 50 0000 C CNN +F 1 "VPLOT8_1" H 7500 3400 50 0000 C CNN + 1 7350 3300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG02" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2950 +F 0 "U2" H 5400 3050 50 0000 C CNN +F 1 "IPLOT" H 5700 3050 50 0000 C CNN + 1 5550 2950 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6150 2950 +F 0 "R2" V 6230 2950 50 0000 C CNN +F 1 "9000" V 6150 2950 50 0000 C CNN + 1 6150 2950 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR03" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "1000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir new file mode 100644 index 0000000..cbcca2f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir @@ -0,0 +1,16 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wednesday 17 April 2013 12:50:50 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +R3 6 0 1000 +v1 5 0 SINE +U3 6 VPLOT8_1 +U1 4 2 IPLOT +U2 2 3 IPLOT +R2 6 3 9000 +R1 4 5 1000 +X1 2 0 6 UA741 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.ckt new file mode 100644 index 0000000..6843d47 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.ckt @@ -0,0 +1,17 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 17 april 2013 12:50:50 pm ist +.include ua741.sub + +r3 6 0 1000 +v1 5 0 sine(0 5 50 0 0) +* Plotting option vplot8_1 +V_u1 4 2 0 +V_u2 2 3 0 +r2 6 3 9000 +r1 4 5 1000 +x1 2 0 6 ua741 + +.tran 10e-03 20e-03 0e-00 +.plot v(6) +.plot i(V_u1) +.plot i(V_u2) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.out new file mode 100644 index 0000000..9e60789 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.out @@ -0,0 +1,22 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 17 april 2013 12:50:50 pm ist +.include ua741.sub + +r3 6 0 1000 +v1 5 0 sine(0 5 50 0 0) +* Plotting option vplot8_1 +V_u1 4 2 0 +V_u2 2 3 0 +r2 6 3 9000 +r1 4 5 1000 +x1 2 0 6 ua741 + +.tran 10e-03 20e-03 0e-00 + +* Control Statements +.control +run +plot v(6) +plot i(V_u1) +plot i(V_u2) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.pro new file mode 100644 index 0000000..ead436b --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.pro @@ -0,0 +1,74 @@ +update=Wednesday 17 April 2013 11:37:31 AM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.proj new file mode 100644 index 0000000..8554126 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.proj @@ -0,0 +1 @@ +schematicFile example_5.6.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.sch new file mode 100644 index 0000000..73864f6 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.sch @@ -0,0 +1,183 @@ +EESchema Schematic File Version 2 date Wednesday 17 April 2013 12:50:53 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.6-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 4050 4100 7050 4100 +Wire Wire Line + 7050 4100 7050 4000 +Wire Wire Line + 7050 3300 6350 3300 +Wire Wire Line + 6400 2950 7050 2950 +Connection ~ 7050 3300 +Connection ~ 6350 3300 +Connection ~ 5350 4100 +Wire Wire Line + 4150 3200 4050 3200 +Wire Wire Line + 5900 2950 5800 2950 +Wire Wire Line + 5350 3200 5250 3200 +Wire Wire Line + 5300 2950 5300 3200 +Connection ~ 5300 3200 +Wire Wire Line + 5350 4200 5350 3400 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 7050 2950 7050 3500 +$Comp +L R R3 +U 1 1 516E4D07 +P 7050 3750 +F 0 "R3" V 7130 3750 50 0000 C CNN +F 1 "1000" V 7050 3750 50 0000 C CNN + 1 7050 3750 + 1 0 0 -1 +$EndComp +$Comp +L SINE v1 +U 1 1 516E3BC9 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "SINE" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 516D11A2 +P 5350 4100 +F 0 "#FLG01" H 5350 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN + 1 5350 4100 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7350 3300 +F 0 "U3" H 7200 3400 50 0000 C CNN +F 1 "VPLOT8_1" H 7500 3400 50 0000 C CNN + 1 7350 3300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG02" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2950 +F 0 "U2" H 5400 3050 50 0000 C CNN +F 1 "IPLOT" H 5700 3050 50 0000 C CNN + 1 5550 2950 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6150 2950 +F 0 "R2" V 6230 2950 50 0000 C CNN +F 1 "9000" V 6150 2950 50 0000 C CNN + 1 6150 2950 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR03" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "1000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.bak new file mode 100644 index 0000000..6be9280 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir new file mode 100644 index 0000000..de79742 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.ckt new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.out new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.out @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.pro new file mode 100644 index 0000000..1235eb1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.pro @@ -0,0 +1,82 @@ +update=Wednesday 17 April 2013 12:51:39 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice +LibName39=/home/holy/OSCAD/library/analogSpice +LibName40=/home/holy/OSCAD/library/analogXSpice +LibName41=/home/holy/OSCAD/library/convergenceAidSpice +LibName42=/home/holy/OSCAD/library/converterSpice +LibName43=/home/holy/OSCAD/library/digitalSpice +LibName44=/home/holy/OSCAD/library/digitalXSpice +LibName45=/home/holy/OSCAD/library/linearSpice +LibName46=/home/holy/OSCAD/library/measurementSpice +LibName47=/home/holy/OSCAD/library/portSpice +LibName48=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sch new file mode 100644 index 0000000..7dfc5e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sub new file mode 100644 index 0000000..1edba9f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sub @@ -0,0 +1,11 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 + +.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/analysis new file mode 100644 index 0000000..234e759 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/analysis @@ -0,0 +1,8 @@ + +.ac lin 10 1Hz 1Meg + + +.end +.control +run +.endc diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7-cache.bak new file mode 100644 index 0000000..bef6862 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7-cache.bak @@ -0,0 +1,127 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 15 May 2013 10:40:53 PM IST +#encoding utf-8 +# +# AC +# +DEF AC AC 0 40 Y Y 1 F N +F0 "AC" -200 100 60 H V C CNN +F1 "AC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7-cache.lib new file mode 100644 index 0000000..a99ee60 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7-cache.lib @@ -0,0 +1,127 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 15 May 2013 10:41:23 PM IST +#encoding utf-8 +# +# AC +# +DEF AC AC 0 40 Y Y 1 F N +F0 "AC" -200 100 60 H V C CNN +F1 "AC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.bak new file mode 100644 index 0000000..5b65555 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.bak @@ -0,0 +1,210 @@ +EESchema Schematic File Version 2 date Wednesday 15 May 2013 10:40:53 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.7-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L AC AC1 +U 1 1 5193C186 +P 4050 3650 +F 0 "AC1" H 3850 3750 60 0000 C CNN +F 1 "AC" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7050 3500 7050 2950 +Connection ~ 6500 2950 +Wire Wire Line + 6500 2950 6500 2550 +Wire Wire Line + 6500 2550 6300 2550 +Connection ~ 5300 2950 +Wire Wire Line + 5300 2550 5300 3200 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 5350 4200 5350 3400 +Connection ~ 5300 3200 +Wire Wire Line + 5350 3200 5250 3200 +Wire Wire Line + 5900 2950 5800 2950 +Wire Wire Line + 4150 3200 4050 3200 +Connection ~ 5350 4100 +Connection ~ 6350 3300 +Connection ~ 7050 3300 +Wire Wire Line + 7050 2950 6400 2950 +Wire Wire Line + 6350 3300 7050 3300 +Wire Wire Line + 5800 2550 5900 2550 +Wire Wire Line + 4050 4100 7050 4100 +Wire Wire Line + 7050 4100 7050 4000 +Connection ~ 7050 3400 +$Comp +L R R3 +U 1 1 516E71B7 +P 7050 3750 +F 0 "R3" V 7130 3750 50 0000 C CNN +F 1 "R" V 7050 3750 50 0000 C CNN + 1 7050 3750 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG2 +U 1 1 516E6E61 +P 5350 4100 +F 0 "#FLG2" H 5350 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN + 1 5350 4100 + -1 0 0 1 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516E6E43 +P 7350 3400 +F 0 "U3" H 7200 3500 50 0000 C CNN +F 1 "VPLOT8_1" H 7500 3500 50 0000 C CNN + 1 7350 3400 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG1 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG1" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L C C1 +U 1 1 516E6B62 +P 6100 2550 +F 0 "C1" H 6150 2650 50 0000 L CNN +F 1 "1.59n" H 6150 2450 50 0000 L CNN + 1 6100 2550 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516E6B56 +P 5550 2550 +F 0 "U4" H 5400 2650 50 0000 C CNN +F 1 "IPLOT" H 5700 2650 50 0000 C CNN + 1 5550 2550 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2950 +F 0 "U2" H 5400 3050 50 0000 C CNN +F 1 "IPLOT" H 5700 3050 50 0000 C CNN + 1 5550 2950 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6150 2950 +F 0 "R2" V 6230 2950 50 0000 C CNN +F 1 "10000" V 6150 2950 50 0000 C CNN + 1 6150 2950 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR1 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR1" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "1000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir new file mode 100644 index 0000000..944330f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir @@ -0,0 +1,18 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wednesday 15 May 2013 10:41:20 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +v1 6 0 AC +R3 7 0 R +U3 7 VPLOT8_1 +C1 7 3 1.59n +U4 1 3 IPLOT +U1 5 1 IPLOT +U2 1 4 IPLOT +R2 7 4 10000 +R1 5 6 1000 +X1 1 0 7 UA741 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir.ckt new file mode 100644 index 0000000..28de072 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir.ckt @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 15 may 2013 10:41:20 pm ist +.include ua741.sub + +v1 6 0 ac 1 +r3 7 0 r +* Plotting option vplot8_1 +c1 7 3 1.59n +V_u4 1 3 0 +V_u1 5 1 0 +V_u2 1 4 0 +r2 7 4 10000 +r1 5 6 1000 +x1 1 0 7 ua741 + +.ac lin 10 1Hz 1Meg +.plot v(7) +.plot i(V_u4) +.plot i(V_u1) +.plot i(V_u2) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir.out new file mode 100644 index 0000000..9002bf8 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir.out @@ -0,0 +1,25 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 15 may 2013 10:41:20 pm ist +.include ua741.sub + +v1 6 0 ac 1 +r3 7 0 r +* Plotting option vplot8_1 +c1 7 3 1.59n +V_u4 1 3 0 +V_u1 5 1 0 +V_u2 1 4 0 +r2 7 4 10000 +r1 5 6 1000 +x1 1 0 7 ua741 + +.ac lin 10 1Hz 1Meg + +* Control Statements +.control +run +plot v(7) +plot i(V_u4) +plot i(V_u1) +plot i(V_u2) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.pro new file mode 100644 index 0000000..a2b4ce1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.pro @@ -0,0 +1,74 @@ +update=Wednesday 17 April 2013 12:56:50 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.proj new file mode 100644 index 0000000..304c734 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.proj @@ -0,0 +1 @@ +schematicFile example_5.7.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.sch new file mode 100644 index 0000000..d7677e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.sch @@ -0,0 +1,210 @@ +EESchema Schematic File Version 2 date Wednesday 15 May 2013 10:41:23 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.7-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L AC v1 +U 1 1 5193C186 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "AC" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7050 3500 7050 2950 +Connection ~ 6500 2950 +Wire Wire Line + 6500 2950 6500 2550 +Wire Wire Line + 6500 2550 6300 2550 +Connection ~ 5300 2950 +Wire Wire Line + 5300 2550 5300 3200 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 5350 4200 5350 3400 +Connection ~ 5300 3200 +Wire Wire Line + 5350 3200 5250 3200 +Wire Wire Line + 5900 2950 5800 2950 +Wire Wire Line + 4150 3200 4050 3200 +Connection ~ 5350 4100 +Connection ~ 6350 3300 +Connection ~ 7050 3300 +Wire Wire Line + 7050 2950 6400 2950 +Wire Wire Line + 6350 3300 7050 3300 +Wire Wire Line + 5800 2550 5900 2550 +Wire Wire Line + 4050 4100 7050 4100 +Wire Wire Line + 7050 4100 7050 4000 +Connection ~ 7050 3400 +$Comp +L R R3 +U 1 1 516E71B7 +P 7050 3750 +F 0 "R3" V 7130 3750 50 0000 C CNN +F 1 "R" V 7050 3750 50 0000 C CNN + 1 7050 3750 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 516E6E61 +P 5350 4100 +F 0 "#FLG01" H 5350 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN + 1 5350 4100 + -1 0 0 1 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516E6E43 +P 7350 3400 +F 0 "U3" H 7200 3500 50 0000 C CNN +F 1 "VPLOT8_1" H 7500 3500 50 0000 C CNN + 1 7350 3400 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG02" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L C C1 +U 1 1 516E6B62 +P 6100 2550 +F 0 "C1" H 6150 2650 50 0000 L CNN +F 1 "1.59n" H 6150 2450 50 0000 L CNN + 1 6100 2550 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516E6B56 +P 5550 2550 +F 0 "U4" H 5400 2650 50 0000 C CNN +F 1 "IPLOT" H 5700 2650 50 0000 C CNN + 1 5550 2550 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2950 +F 0 "U2" H 5400 3050 50 0000 C CNN +F 1 "IPLOT" H 5700 3050 50 0000 C CNN + 1 5550 2950 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6150 2950 +F 0 "R2" V 6230 2950 50 0000 C CNN +F 1 "10000" V 6150 2950 50 0000 C CNN + 1 6150 2950 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR03" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "1000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.bak new file mode 100644 index 0000000..6be9280 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir new file mode 100644 index 0000000..de79742 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir.ckt new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir.out new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir.out @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.pro new file mode 100644 index 0000000..9aa118e --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.pro @@ -0,0 +1,72 @@ +update=Monday 17 December 2012 06:14:06 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.sch new file mode 100644 index 0000000..7dfc5e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.sub new file mode 100644 index 0000000..1edba9f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.sub @@ -0,0 +1,11 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 + +.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/analysis new file mode 100644 index 0000000..64c6d69 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/analysis @@ -0,0 +1 @@ +.tran 1e-03 2e-03 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.1.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.1.sch new file mode 100644 index 0000000..d6f19aa --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.1.sch @@ -0,0 +1,172 @@ +EESchema Schematic File Version 2 date Wednesday 17 April 2013 05:15:51 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5350 4100 4050 4100 +Wire Wire Line + 6350 3300 7050 3300 +Wire Wire Line + 6400 2950 7050 2950 +Connection ~ 7050 3300 +Connection ~ 6350 3300 +Connection ~ 5350 4100 +Wire Wire Line + 4150 3200 4050 3200 +Wire Wire Line + 5900 2950 5800 2950 +Wire Wire Line + 5350 3200 5250 3200 +Wire Wire Line + 5300 2950 5300 3200 +Connection ~ 5300 3200 +Wire Wire Line + 5350 4200 5350 3400 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 7050 2950 7050 3300 +$Comp +L SINE v1 +U 1 1 516E3AE9 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "SINE" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 516D11A2 +P 5350 4100 +F 0 "#FLG01" H 5350 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN + 1 5350 4100 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7350 3300 +F 0 "U3" H 7200 3400 50 0000 C CNN +F 1 "VPLOT8_1" H 7500 3400 50 0000 C CNN + 1 7350 3300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG02" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2950 +F 0 "U2" H 5400 3050 50 0000 C CNN +F 1 "IPLOT" H 5700 3050 50 0000 C CNN + 1 5550 2950 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6150 2950 +F 0 "R2" V 6230 2950 50 0000 C CNN +F 1 "10000" V 6150 2950 50 0000 C CNN + 1 6150 2950 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR03" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "1000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8-cache.bak new file mode 100644 index 0000000..969d8ac --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8-cache.bak @@ -0,0 +1,157 @@ +EESchema-LIBRARY Version 2.3 Date: Thursday 18 April 2013 09:19:41 AM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8 +# +DEF vplot8 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -300 0 200 R 40 40 1 1 O +X - 9 300 0 200 L 40 40 1 1 O +X + 2 -300 0 200 R 40 40 2 1 O +X - 10 300 0 200 L 40 40 2 1 O +X + 3 -300 0 200 R 40 40 3 1 O +X - 11 300 0 200 L 40 40 3 1 O +X + 4 -300 0 200 R 40 40 4 1 O +X - 12 300 0 200 L 40 40 4 1 O +X + 5 -300 0 200 R 40 40 5 1 O +X - 13 300 0 200 L 40 40 5 1 O +X + 6 -300 0 200 R 40 40 6 1 O +X - 14 300 0 200 L 40 40 6 1 O +X + 7 -300 0 200 R 40 40 7 1 O +X - 15 300 0 200 L 40 40 7 1 O +X + 8 -300 0 200 R 40 40 8 1 O +X - 16 300 0 200 L 40 40 8 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8-cache.lib new file mode 100644 index 0000000..32852ba --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8-cache.lib @@ -0,0 +1,157 @@ +EESchema-LIBRARY Version 2.3 Date: Thursday 18 April 2013 10:25:50 AM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8 +# +DEF vplot8 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -300 0 200 R 40 40 1 1 O +X - 9 300 0 200 L 40 40 1 1 O +X + 2 -300 0 200 R 40 40 2 1 O +X - 10 300 0 200 L 40 40 2 1 O +X + 3 -300 0 200 R 40 40 3 1 O +X - 11 300 0 200 L 40 40 3 1 O +X + 4 -300 0 200 R 40 40 4 1 O +X - 12 300 0 200 L 40 40 4 1 O +X + 5 -300 0 200 R 40 40 5 1 O +X - 13 300 0 200 L 40 40 5 1 O +X + 6 -300 0 200 R 40 40 6 1 O +X - 14 300 0 200 L 40 40 6 1 O +X + 7 -300 0 200 R 40 40 7 1 O +X - 15 300 0 200 L 40 40 7 1 O +X + 8 -300 0 200 R 40 40 8 1 O +X - 16 300 0 200 L 40 40 8 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.bak new file mode 100644 index 0000000..a102621 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.bak @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Thursday 18 April 2013 09:19:41 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.8-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "18 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 3300 3700 3300 4300 +Wire Wire Line + 3300 3100 3300 2850 +Wire Wire Line + 3300 2850 4200 2850 +Wire Wire Line + 4200 2850 4200 3200 +Wire Wire Line + 5800 2600 5900 2600 +Wire Wire Line + 4050 4100 5350 4100 +Wire Wire Line + 6350 3300 7050 3300 +Wire Wire Line + 7050 2950 6400 2950 +Connection ~ 7050 3300 +Connection ~ 6350 3300 +Connection ~ 5350 4100 +Wire Wire Line + 4150 3200 4050 3200 +Wire Wire Line + 5900 2950 5800 2950 +Wire Wire Line + 5250 3200 5350 3200 +Connection ~ 5300 3200 +Wire Wire Line + 5350 3400 5350 4200 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 5300 3200 5300 2600 +Connection ~ 5300 2950 +Wire Wire Line + 6300 2600 7050 2600 +Wire Wire Line + 7050 2600 7050 3300 +Connection ~ 7050 2950 +Connection ~ 4100 3200 +Wire Wire Line + 4250 4100 4250 4300 +Connection ~ 4250 4100 +Wire Wire Line + 4250 4300 3300 4300 +$Comp +L VPLOT8 U5 +U 1 1 516F6D28 +P 3300 3400 +F 0 "U5" H 3150 3500 50 0000 C CNN +F 1 "VPLOT8" H 3450 3500 50 0000 C CNN + 1 3300 3400 + 0 1 1 0 +$EndComp +$Comp +L PULSE v1 +U 1 1 516E8CD4 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "PULSE" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +$Comp +L C C1 +U 1 1 516E8BE7 +P 6100 2600 +F 0 "C1" H 6150 2700 50 0000 L CNN +F 1 "10n" H 6150 2500 50 0000 L CNN + 1 6100 2600 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516E8BCF +P 5550 2600 +F 0 "U4" H 5400 2700 50 0000 C CNN +F 1 "IPLOT" H 5700 2700 50 0000 C CNN + 1 5550 2600 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG2 +U 1 1 516D11A2 +P 5350 4100 +F 0 "#FLG2" H 5350 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN + 1 5350 4100 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7350 3300 +F 0 "U3" H 7200 3400 50 0000 C CNN +F 1 "VPLOT8_1" H 7500 3400 50 0000 C CNN + 1 7350 3300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG1 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG1" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2950 +F 0 "U2" H 5400 3050 50 0000 C CNN +F 1 "IPLOT" H 5700 3050 50 0000 C CNN + 1 5550 2950 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6150 2950 +F 0 "R2" V 6230 2950 50 0000 C CNN +F 1 "1000000" V 6150 2950 50 0000 C CNN + 1 6150 2950 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR1 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR1" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "10000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir new file mode 100644 index 0000000..b53502b --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir @@ -0,0 +1,18 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Thursday 18 April 2013 10:25:46 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U5 5 0 VPLOT8 +v1 5 0 PULSE +C1 6 1 10n +U4 2 1 IPLOT +U3 6 VPLOT8_1 +U1 4 2 IPLOT +U2 2 3 IPLOT +R2 6 3 1000000 +R1 4 5 10000 +X1 2 0 6 UA741 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir.ckt new file mode 100644 index 0000000..63570ef --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir.ckt @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: thursday 18 april 2013 10:25:46 am ist +.include ua741.sub + +v1 5 0 pulse(1 0 0 0 0 0.001 0.002) +c1 6 1 10n +V_u4 2 1 0 +* Plotting option vplot8_1 +V_u1 4 2 0 +V_u2 2 3 0 +r2 6 3 1000000 +r1 4 5 10000 +x1 2 0 6 ua741 + +.tran 1e-03 2e-03 0e-00 +.plot v(5) +.plot i(V_u4) +.plot v(6) +.plot i(V_u1) +.plot i(V_u2) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir.out new file mode 100644 index 0000000..ed95f2f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir.out @@ -0,0 +1,25 @@ +* eeschema netlist version 1.1 (spice format) creation date: thursday 18 april 2013 10:25:46 am ist +.include ua741.sub + +v1 5 0 pulse(1 0 0 0 0 0.001 0.002) +c1 6 1 10n +V_u4 2 1 0 +* Plotting option vplot8_1 +V_u1 4 2 0 +V_u2 2 3 0 +r2 6 3 1000000 +r1 4 5 10000 +x1 2 0 6 ua741 + +.tran 1e-03 2e-03 0e-00 + +* Control Statements +.control +run +plot v(5) +plot i(V_u4) +plot v(6) +plot i(V_u1) +plot i(V_u2) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.pro new file mode 100644 index 0000000..62130f3 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.pro @@ -0,0 +1,74 @@ +update=Wednesday 17 April 2013 05:14:42 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.proj new file mode 100644 index 0000000..a7ce942 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.proj @@ -0,0 +1 @@ +schematicFile example_5.8.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.sch new file mode 100644 index 0000000..976a836 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.sch @@ -0,0 +1,214 @@ +EESchema Schematic File Version 2 date Thursday 18 April 2013 10:25:50 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.8-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "18 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 4100 3200 4100 2950 +Wire Wire Line + 4100 2950 4200 2950 +Wire Wire Line + 4200 2950 4200 2850 +Wire Wire Line + 4250 4300 3300 4300 +Connection ~ 4250 4100 +Wire Wire Line + 4250 4300 4250 4100 +Connection ~ 4100 3200 +Connection ~ 7050 2950 +Wire Wire Line + 7050 2600 7050 3300 +Wire Wire Line + 7050 2600 6300 2600 +Connection ~ 5300 2950 +Wire Wire Line + 5300 3200 5300 2600 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 5350 3400 5350 4200 +Connection ~ 5300 3200 +Wire Wire Line + 5250 3200 5350 3200 +Wire Wire Line + 5900 2950 5800 2950 +Wire Wire Line + 4150 3200 4050 3200 +Connection ~ 5350 4100 +Connection ~ 6350 3300 +Connection ~ 7050 3300 +Wire Wire Line + 7050 2950 6400 2950 +Wire Wire Line + 7050 3300 6350 3300 +Wire Wire Line + 4050 4100 5350 4100 +Wire Wire Line + 5800 2600 5900 2600 +Wire Wire Line + 3300 4300 3300 3700 +Wire Wire Line + 3300 3100 3300 2850 +Wire Wire Line + 3300 2850 4200 2850 +$Comp +L VPLOT8 U5 +U 1 1 516F6D28 +P 3300 3400 +F 0 "U5" H 3150 3500 50 0000 C CNN +F 1 "VPLOT8" H 3450 3500 50 0000 C CNN + 1 3300 3400 + 0 1 1 0 +$EndComp +$Comp +L PULSE v1 +U 1 1 516E8CD4 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "PULSE" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +$Comp +L C C1 +U 1 1 516E8BE7 +P 6100 2600 +F 0 "C1" H 6150 2700 50 0000 L CNN +F 1 "10n" H 6150 2500 50 0000 L CNN + 1 6100 2600 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516E8BCF +P 5550 2600 +F 0 "U4" H 5400 2700 50 0000 C CNN +F 1 "IPLOT" H 5700 2700 50 0000 C CNN + 1 5550 2600 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7350 3300 +F 0 "U3" H 7200 3400 50 0000 C CNN +F 1 "VPLOT8_1" H 7500 3400 50 0000 C CNN + 1 7350 3300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG01" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2950 +F 0 "U2" H 5400 3050 50 0000 C CNN +F 1 "IPLOT" H 5700 3050 50 0000 C CNN + 1 5550 2950 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6150 2950 +F 0 "R2" V 6230 2950 50 0000 C CNN +F 1 "1000000" V 6150 2950 50 0000 C CNN + 1 6150 2950 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR02" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "10000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.bak new file mode 100644 index 0000000..6be9280 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir new file mode 100644 index 0000000..de79742 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir.ckt new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir.out new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir.out @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.pro new file mode 100644 index 0000000..9aa118e --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.pro @@ -0,0 +1,72 @@ +update=Monday 17 December 2012 06:14:06 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.sch new file mode 100644 index 0000000..7dfc5e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.sub new file mode 100644 index 0000000..1edba9f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.sub @@ -0,0 +1,11 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 + +.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/analysis new file mode 100644 index 0000000..48302a3 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/analysis @@ -0,0 +1 @@ +.tran 2e-03 4e-03 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir new file mode 100644 index 0000000..d30b232 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir @@ -0,0 +1,24 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Thursday 18 April 2013 10:53:39 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +v1 4 0 PULSE +v2 11 0 10V +U3 8 3 VPLOT8_1 +R5 13 3 10000 +R4 0 13 10000 +R3 1 11 10000 +U5 8 2 IPLOT +Q2 1 1 2 NPN +X2 1 13 3 UA741 +U4 10 8 IPLOT +Q1 10 0 9 NPN +U1 6 7 IPLOT +U2 7 9 IPLOT +R2 8 5 10000 +R1 6 4 1000 +X1 7 0 5 UA741 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir.ckt new file mode 100644 index 0000000..0decb7c --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir.ckt @@ -0,0 +1,27 @@ +* eeschema netlist version 1.1 (spice format) creation date: thursday 18 april 2013 10:53:39 am ist +.include ua741.sub + +v1 4 0 pulse(0 1 0.002 0.004) +v2 11 0 10v +* Plotting option vplot8_1 +r5 13 3 10000 +r4 0 13 10000 +r3 1 11 10000 +V_u5 8 2 0 +q2 2 1 1 npn +x2 1 13 3 ua741 +V_u4 10 8 0 +q1 10 0 9 npn +V_u1 6 7 0 +V_u2 7 9 0 +r2 8 5 10000 +r1 6 4 1000 +x1 7 0 5 ua741 + +.tran 2e-03 4e-03 0e-00 +.plot v(8) v(3) +.plot i(V_u5) +.plot i(V_u4) +.plot i(V_u1) +.plot i(V_u2) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir.out new file mode 100644 index 0000000..f4b917f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir.out @@ -0,0 +1,32 @@ +* eeschema netlist version 1.1 (spice format) creation date: thursday 18 april 2013 10:53:39 am ist +.include ua741.sub + +v1 4 0 pulse(0 1 0.002 0.004) +v2 11 0 10v +* Plotting option vplot8_1 +r5 13 3 10000 +r4 0 13 10000 +r3 1 11 10000 +V_u5 8 2 0 +q2 2 1 1 npn +x2 1 13 3 ua741 +V_u4 10 8 0 +q1 10 0 9 npn +V_u1 6 7 0 +V_u2 7 9 0 +r2 8 5 10000 +r1 6 4 1000 +x1 7 0 5 ua741 + +.tran 2e-03 4e-03 0e-00 + +* Control Statements +.control +run +plot v(8) v(3) +plot i(V_u5) +plot i(V_u4) +plot i(V_u1) +plot i(V_u2) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.pro new file mode 100644 index 0000000..6a09490 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.pro @@ -0,0 +1,74 @@ +update=Thursday 18 April 2013 10:31:10 AM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.proj new file mode 100644 index 0000000..da8b8d1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.proj @@ -0,0 +1 @@ +schematicFile example_5.9.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.sch new file mode 100644 index 0000000..481506c --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.sch @@ -0,0 +1,324 @@ +EESchema Schematic File Version 2 date Thursday 18 April 2013 10:52:19 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "18 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L GND #PWR01 +U 1 1 516F8096 +P 6150 2850 +F 0 "#PWR01" H 6150 2850 30 0001 C CNN +F 1 "GND" H 6150 2780 30 0001 C CNN + 1 6150 2850 + 1 0 0 -1 +$EndComp +Connection ~ 6150 2750 +$Comp +L PWR_FLAG #FLG02 +U 1 1 516F807F +P 6150 2750 +F 0 "#FLG02" H 6150 3020 30 0001 C CNN +F 1 "PWR_FLAG" H 6150 2980 30 0000 C CNN + 1 6150 2750 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 6150 2700 6150 2850 +Wire Wire Line + 10200 3750 10200 5050 +Wire Wire Line + 10200 2850 10200 2400 +Wire Wire Line + 10200 2400 8100 2400 +Wire Wire Line + 9250 3700 9400 3700 +Wire Wire Line + 8250 3800 8250 4100 +Connection ~ 8100 3300 +Wire Wire Line + 8100 3050 8100 3600 +Wire Wire Line + 7900 3600 8250 3600 +Wire Wire Line + 7150 3300 6950 3300 +Wire Wire Line + 6350 2400 6400 2400 +Wire Wire Line + 5300 2400 5300 3200 +Wire Wire Line + 6350 3300 6450 3300 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 5350 4200 5350 3400 +Connection ~ 5300 3200 +Wire Wire Line + 5350 3200 5250 3200 +Wire Wire Line + 4150 3200 4050 3200 +Connection ~ 5350 4100 +Connection ~ 6350 3300 +Connection ~ 7050 3300 +Wire Wire Line + 5350 4100 4050 4100 +Wire Wire Line + 5800 2400 5950 2400 +Wire Wire Line + 6900 2400 7050 2400 +Wire Wire Line + 7050 2400 7050 3300 +Wire Wire Line + 7650 3300 7700 3300 +Connection ~ 8100 3600 +Wire Wire Line + 8100 2400 8100 2550 +Wire Wire Line + 8250 4000 8450 4000 +Connection ~ 8250 4000 +Wire Wire Line + 9300 3700 9300 4000 +Wire Wire Line + 9300 4000 8950 4000 +Connection ~ 9300 3700 +Connection ~ 9400 3700 +Connection ~ 8100 2400 +Wire Wire Line + 10200 5050 8250 5050 +Wire Wire Line + 8250 5250 8250 4600 +Connection ~ 8250 5050 +Connection ~ 8250 5150 +$Comp +L GND #PWR03 +U 1 1 516F8034 +P 8250 5250 +F 0 "#PWR03" H 8250 5250 30 0001 C CNN +F 1 "GND" H 8250 5180 30 0001 C CNN + 1 8250 5250 + 1 0 0 -1 +$EndComp +$Comp +L PULSE v1 +U 1 1 516F801F +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "PULSE" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 516F7FED +P 10200 3300 +F 0 "v2" H 10000 3400 60 0000 C CNN +F 1 "10V" H 10000 3250 60 0000 C CNN +F 2 "R1" H 9900 3300 60 0000 C CNN + 1 10200 3300 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U3 +U 2 1 516F7F85 +P 9400 4000 +F 0 "U3" H 9250 4100 50 0000 C CNN +F 1 "VPLOT8_1" H 9550 4100 50 0000 C CNN + 2 9400 4000 + -1 0 0 1 +$EndComp +$Comp +L R R5 +U 1 1 516F7F66 +P 8700 4000 +F 0 "R5" V 8780 4000 50 0000 C CNN +F 1 "10000" V 8700 4000 50 0000 C CNN + 1 8700 4000 + 0 -1 -1 0 +$EndComp +$Comp +L R R4 +U 1 1 516F7F56 +P 8250 4350 +F 0 "R4" V 8330 4350 50 0000 C CNN +F 1 "10000" V 8250 4350 50 0000 C CNN + 1 8250 4350 + -1 0 0 1 +$EndComp +$Comp +L R R3 +U 1 1 516F7F35 +P 8100 2800 +F 0 "R3" V 8180 2800 50 0000 C CNN +F 1 "10000" V 8100 2800 50 0000 C CNN + 1 8100 2800 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U5 +U 1 1 516F7EEB +P 7400 3300 +F 0 "U5" H 7250 3400 50 0000 C CNN +F 1 "IPLOT" H 7550 3400 50 0000 C CNN + 1 7400 3300 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q2 +U 1 1 516F7EDC +P 7900 3400 +F 0 "Q2" H 7900 3250 50 0000 R CNN +F 1 "NPN" H 7900 3550 50 0000 R CNN + 1 7900 3400 + 0 -1 -1 0 +$EndComp +$Comp +L UA741 X2 +U 1 1 516F7ED1 +P 8750 3700 +F 0 "X2" H 8900 3850 60 0000 C CNN +F 1 "UA741" H 8900 3950 60 0000 C CNN + 1 8750 3700 + 1 0 0 1 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516F7EB1 +P 6650 2400 +F 0 "U4" H 6500 2500 50 0000 C CNN +F 1 "IPLOT" H 6800 2500 50 0000 C CNN + 1 6650 2400 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 516F7E9D +P 6150 2500 +F 0 "Q1" H 6150 2350 50 0000 R CNN +F 1 "NPN" H 6150 2650 50 0000 R CNN + 1 6150 2500 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7050 3600 +F 0 "U3" H 6900 3700 50 0000 C CNN +F 1 "VPLOT8_1" H 7200 3700 50 0000 C CNN + 1 7050 3600 + -1 0 0 1 +$EndComp +$Comp +L PWR_FLAG #FLG04 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG04" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2400 +F 0 "U2" H 5400 2500 50 0000 C CNN +F 1 "IPLOT" H 5700 2500 50 0000 C CNN + 1 5550 2400 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6700 3300 +F 0 "R2" V 6780 3300 50 0000 C CNN +F 1 "10000" V 6700 3300 50 0000 C CNN + 1 6700 3300 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR05 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR05" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "1000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.bak new file mode 100644 index 0000000..6be9280 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir new file mode 100644 index 0000000..de79742 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir.ckt new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir.out new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir.out @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.pro new file mode 100644 index 0000000..df98e42 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.pro @@ -0,0 +1,82 @@ +update=Thursday 18 April 2013 01:48:22 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice +LibName39=/home/holy/OSCAD/library/analogSpice +LibName40=/home/holy/OSCAD/library/analogXSpice +LibName41=/home/holy/OSCAD/library/convergenceAidSpice +LibName42=/home/holy/OSCAD/library/converterSpice +LibName43=/home/holy/OSCAD/library/digitalSpice +LibName44=/home/holy/OSCAD/library/digitalXSpice +LibName45=/home/holy/OSCAD/library/linearSpice +LibName46=/home/holy/OSCAD/library/measurementSpice +LibName47=/home/holy/OSCAD/library/portSpice +LibName48=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.sch new file mode 100644 index 0000000..7dfc5e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.sub new file mode 100644 index 0000000..1edba9f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.sub @@ -0,0 +1,11 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 + +.ends ua741
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