diff options
Diffstat (limited to 'OSCAD/Examples/sedra_smith/chapter_5/example_5.6')
17 files changed, 1256 insertions, 0 deletions
diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/analysis new file mode 100644 index 0000000..c9183fa --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/analysis @@ -0,0 +1 @@ +.tran 10e-03 20e-03 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.bak new file mode 100644 index 0000000..79f0251 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.bak @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 17 April 2013 11:57:44 AM IST +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.lib new file mode 100644 index 0000000..951b224 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.lib @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 17 April 2013 12:50:53 PM IST +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.bak new file mode 100644 index 0000000..9eaa078 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.bak @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 date Wednesday 17 April 2013 11:57:44 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L SINE v1 +U 1 1 516E3BC9 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "SINE" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 4100 4050 4100 +Wire Wire Line + 6350 3300 7050 3300 +Wire Wire Line + 6400 2950 7050 2950 +Connection ~ 7050 3300 +Connection ~ 6350 3300 +Connection ~ 5350 4100 +Wire Wire Line + 4150 3200 4050 3200 +Wire Wire Line + 5900 2950 5800 2950 +Wire Wire Line + 5350 3200 5250 3200 +Wire Wire Line + 5300 2950 5300 3200 +Connection ~ 5300 3200 +Wire Wire Line + 5350 4200 5350 3400 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 7050 2950 7050 3300 +$Comp +L PWR_FLAG #FLG01 +U 1 1 516D11A2 +P 5350 4100 +F 0 "#FLG01" H 5350 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN + 1 5350 4100 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7350 3300 +F 0 "U3" H 7200 3400 50 0000 C CNN +F 1 "VPLOT8_1" H 7500 3400 50 0000 C CNN + 1 7350 3300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG02" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2950 +F 0 "U2" H 5400 3050 50 0000 C CNN +F 1 "IPLOT" H 5700 3050 50 0000 C CNN + 1 5550 2950 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6150 2950 +F 0 "R2" V 6230 2950 50 0000 C CNN +F 1 "9000" V 6150 2950 50 0000 C CNN + 1 6150 2950 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR03" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "1000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir new file mode 100644 index 0000000..cbcca2f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir @@ -0,0 +1,16 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wednesday 17 April 2013 12:50:50 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +R3 6 0 1000 +v1 5 0 SINE +U3 6 VPLOT8_1 +U1 4 2 IPLOT +U2 2 3 IPLOT +R2 6 3 9000 +R1 4 5 1000 +X1 2 0 6 UA741 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.ckt new file mode 100644 index 0000000..6843d47 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.ckt @@ -0,0 +1,17 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 17 april 2013 12:50:50 pm ist +.include ua741.sub + +r3 6 0 1000 +v1 5 0 sine(0 5 50 0 0) +* Plotting option vplot8_1 +V_u1 4 2 0 +V_u2 2 3 0 +r2 6 3 9000 +r1 4 5 1000 +x1 2 0 6 ua741 + +.tran 10e-03 20e-03 0e-00 +.plot v(6) +.plot i(V_u1) +.plot i(V_u2) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.out new file mode 100644 index 0000000..9e60789 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.out @@ -0,0 +1,22 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 17 april 2013 12:50:50 pm ist +.include ua741.sub + +r3 6 0 1000 +v1 5 0 sine(0 5 50 0 0) +* Plotting option vplot8_1 +V_u1 4 2 0 +V_u2 2 3 0 +r2 6 3 9000 +r1 4 5 1000 +x1 2 0 6 ua741 + +.tran 10e-03 20e-03 0e-00 + +* Control Statements +.control +run +plot v(6) +plot i(V_u1) +plot i(V_u2) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.pro new file mode 100644 index 0000000..ead436b --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.pro @@ -0,0 +1,74 @@ +update=Wednesday 17 April 2013 11:37:31 AM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.proj new file mode 100644 index 0000000..8554126 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.proj @@ -0,0 +1 @@ +schematicFile example_5.6.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.sch new file mode 100644 index 0000000..73864f6 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.sch @@ -0,0 +1,183 @@ +EESchema Schematic File Version 2 date Wednesday 17 April 2013 12:50:53 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.6-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 4050 4100 7050 4100 +Wire Wire Line + 7050 4100 7050 4000 +Wire Wire Line + 7050 3300 6350 3300 +Wire Wire Line + 6400 2950 7050 2950 +Connection ~ 7050 3300 +Connection ~ 6350 3300 +Connection ~ 5350 4100 +Wire Wire Line + 4150 3200 4050 3200 +Wire Wire Line + 5900 2950 5800 2950 +Wire Wire Line + 5350 3200 5250 3200 +Wire Wire Line + 5300 2950 5300 3200 +Connection ~ 5300 3200 +Wire Wire Line + 5350 4200 5350 3400 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 7050 2950 7050 3500 +$Comp +L R R3 +U 1 1 516E4D07 +P 7050 3750 +F 0 "R3" V 7130 3750 50 0000 C CNN +F 1 "1000" V 7050 3750 50 0000 C CNN + 1 7050 3750 + 1 0 0 -1 +$EndComp +$Comp +L SINE v1 +U 1 1 516E3BC9 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "SINE" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 516D11A2 +P 5350 4100 +F 0 "#FLG01" H 5350 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN + 1 5350 4100 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7350 3300 +F 0 "U3" H 7200 3400 50 0000 C CNN +F 1 "VPLOT8_1" H 7500 3400 50 0000 C CNN + 1 7350 3300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG02" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2950 +F 0 "U2" H 5400 3050 50 0000 C CNN +F 1 "IPLOT" H 5700 3050 50 0000 C CNN + 1 5550 2950 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6150 2950 +F 0 "R2" V 6230 2950 50 0000 C CNN +F 1 "9000" V 6150 2950 50 0000 C CNN + 1 6150 2950 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR03" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "1000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.bak new file mode 100644 index 0000000..6be9280 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir new file mode 100644 index 0000000..de79742 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.ckt new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.out new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.out @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.pro new file mode 100644 index 0000000..1235eb1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.pro @@ -0,0 +1,82 @@ +update=Wednesday 17 April 2013 12:51:39 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice +LibName39=/home/holy/OSCAD/library/analogSpice +LibName40=/home/holy/OSCAD/library/analogXSpice +LibName41=/home/holy/OSCAD/library/convergenceAidSpice +LibName42=/home/holy/OSCAD/library/converterSpice +LibName43=/home/holy/OSCAD/library/digitalSpice +LibName44=/home/holy/OSCAD/library/digitalXSpice +LibName45=/home/holy/OSCAD/library/linearSpice +LibName46=/home/holy/OSCAD/library/measurementSpice +LibName47=/home/holy/OSCAD/library/portSpice +LibName48=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sch new file mode 100644 index 0000000..7dfc5e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sub new file mode 100644 index 0000000..1edba9f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sub @@ -0,0 +1,11 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 + +.ends ua741
\ No newline at end of file |