diff options
Diffstat (limited to 'OSCAD/Examples/sedra_smith/chapter_3/example_3.1')
11 files changed, 657 insertions, 0 deletions
diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/analysis new file mode 100644 index 0000000..395e205 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/analysis @@ -0,0 +1 @@ +.dc v2 0e-00 15e-00 15e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1-cache.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1-cache.bak new file mode 100644 index 0000000..3c23bc8 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1-cache.bak @@ -0,0 +1,97 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 15 May 2013 06:57:20 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1-cache.lib new file mode 100644 index 0000000..b1e32d7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1-cache.lib @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 15 May 2013 06:59:23 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.bak new file mode 100644 index 0000000..9b63b41 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.bak @@ -0,0 +1,154 @@ +EESchema Schematic File Version 2 date Wednesday 15 May 2013 06:57:20 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_3.1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5750 5350 5750 5950 +Connection ~ 4300 4400 +Connection ~ 5750 4100 +Wire Wire Line + 4300 4500 4300 4400 +Wire Wire Line + 4300 4400 5450 4400 +Connection ~ 4750 4400 +Wire Wire Line + 4750 4600 4750 4050 +Wire Wire Line + 4750 3150 4750 2750 +Wire Wire Line + 4750 2750 5750 2750 +Wire Wire Line + 5750 4600 5750 4850 +Wire Wire Line + 4750 5500 4750 5950 +Wire Wire Line + 4750 5950 5750 5950 +Wire Wire Line + 5750 4200 5750 3250 +$Comp +L DC v1 +U 1 1 517A27AF +P 4750 3600 +F 0 "v1" H 4550 3700 60 0000 C CNN +F 1 "DC" H 4550 3550 60 0000 C CNN +F 2 "R1" H 4450 3600 60 0000 C CNN + 1 4750 3600 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 517A278C +P 4750 5050 +F 0 "v2" H 4550 5150 60 0000 C CNN +F 1 "DC" H 4550 5000 60 0000 C CNN +F 2 "R1" H 4450 5050 60 0000 C CNN + 1 4750 5050 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 5178C864 +P 6050 4100 +F 0 "U1" H 5900 4200 50 0000 C CNN +F 1 "VPLOT8_1" H 6200 4200 50 0000 C CNN + 1 6050 4100 + 0 1 1 0 +$EndComp +$Comp +L NPN Q1 +U 1 1 5178C812 +P 5650 4400 +F 0 "Q1" H 5650 4250 50 0000 R CNN +F 1 "NPN" H 5650 4550 50 0000 R CNN + 1 5650 4400 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 516BDAF0 +P 4300 4400 +F 0 "#FLG01" H 4300 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 4300 4630 30 0000 C CNN + 1 4300 4400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 516BDAE0 +P 4300 4500 +F 0 "#PWR02" H 4300 4500 30 0001 C CNN +F 1 "GND" H 4300 4430 30 0001 C CNN + 1 4300 4500 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516BD9B5 +P 5750 3000 +F 0 "R1" V 5830 3000 50 0000 C CNN +F 1 "5k" V 5750 3000 50 0000 C CNN + 1 5750 3000 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516BD9A9 +P 5750 5100 +F 0 "R2" V 5850 5100 50 0000 C CNN +F 1 "7.07k" V 5750 5100 50 0000 C CNN + 1 5750 5100 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir new file mode 100644 index 0000000..bdacb65 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wednesday 15 May 2013 06:59:18 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U2 4 3 IPLOT +v1 1 0 DC +v2 0 5 DC +U1 3 VPLOT8_1 +Q1 2 0 3 NPN +R1 1 4 5k +R2 2 5 7.07k + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir.ckt new file mode 100644 index 0000000..055c4d2 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir.ckt @@ -0,0 +1,15 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 15 may 2013 06:59:18 pm ist +.include npn.lib + +V_u2 4 3 0 +v1 1 0 dc 15 +v2 0 5 dc 15 +* Plotting option vplot8_1 +q1 3 0 2 npn +r1 1 4 5k +r2 2 5 7.07k + +.dc v2 0e-00 15e-00 15e-00 +.plot i(V_u2) +.plot v(3) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir.out new file mode 100644 index 0000000..17c61c2 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 15 may 2013 06:59:18 pm ist +.include npn.lib + +V_u2 4 3 0 +v1 1 0 dc 15 +v2 0 5 dc 15 +* Plotting option vplot8_1 +q1 3 0 2 npn +r1 1 4 5k +r2 2 5 7.07k + +.dc v2 0e-00 15e-00 15e-00 + +* Control Statements +.control +run +plot i(V_u2) +plot v(3) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.pro new file mode 100644 index 0000000..5bf994d --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.pro @@ -0,0 +1,74 @@ +update=Monday 15 April 2013 04:46:53 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.proj new file mode 100644 index 0000000..3a2ba21 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.proj @@ -0,0 +1 @@ +schematicFile example_3.1.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.sch new file mode 100644 index 0000000..7873ea6 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.sch @@ -0,0 +1,165 @@ +EESchema Schematic File Version 2 date Wednesday 15 May 2013 06:59:23 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_3.1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5750 4200 5750 3850 +Wire Wire Line + 5750 5350 5750 5950 +Connection ~ 4300 4400 +Connection ~ 5750 4100 +Wire Wire Line + 4300 4500 4300 4400 +Wire Wire Line + 4300 4400 5450 4400 +Connection ~ 4750 4400 +Wire Wire Line + 4750 4600 4750 4050 +Wire Wire Line + 4750 3150 4750 2750 +Wire Wire Line + 4750 2750 5750 2750 +Wire Wire Line + 5750 4600 5750 4850 +Wire Wire Line + 4750 5500 4750 5950 +Wire Wire Line + 4750 5950 5750 5950 +Wire Wire Line + 5750 3250 5750 3350 +$Comp +L IPLOT U2 +U 1 1 51938D87 +P 5750 3600 +F 0 "U2" H 5600 3700 50 0000 C CNN +F 1 "IPLOT" H 5900 3700 50 0000 C CNN + 1 5750 3600 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 517A27AF +P 4750 3600 +F 0 "v1" H 4550 3700 60 0000 C CNN +F 1 "DC" H 4550 3550 60 0000 C CNN +F 2 "R1" H 4450 3600 60 0000 C CNN + 1 4750 3600 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 517A278C +P 4750 5050 +F 0 "v2" H 4550 5150 60 0000 C CNN +F 1 "DC" H 4550 5000 60 0000 C CNN +F 2 "R1" H 4450 5050 60 0000 C CNN + 1 4750 5050 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 5178C864 +P 6050 4100 +F 0 "U1" H 5900 4200 50 0000 C CNN +F 1 "VPLOT8_1" H 6200 4200 50 0000 C CNN + 1 6050 4100 + 0 1 1 0 +$EndComp +$Comp +L NPN Q1 +U 1 1 5178C812 +P 5650 4400 +F 0 "Q1" H 5650 4250 50 0000 R CNN +F 1 "NPN" H 5650 4550 50 0000 R CNN + 1 5650 4400 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG1 +U 1 1 516BDAF0 +P 4300 4400 +F 0 "#FLG1" H 4300 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 4300 4630 30 0000 C CNN + 1 4300 4400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR1 +U 1 1 516BDAE0 +P 4300 4500 +F 0 "#PWR1" H 4300 4500 30 0001 C CNN +F 1 "GND" H 4300 4430 30 0001 C CNN + 1 4300 4500 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516BD9B5 +P 5750 3000 +F 0 "R1" V 5830 3000 50 0000 C CNN +F 1 "5k" V 5750 3000 50 0000 C CNN + 1 5750 3000 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516BD9A9 +P 5750 5100 +F 0 "R2" V 5850 5100 50 0000 C CNN +F 1 "7.07k" V 5750 5100 50 0000 C CNN + 1 5750 5100 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/npn.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/npn.lib new file mode 100644 index 0000000..1ff6b05 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/npn.lib @@ -0,0 +1,6 @@ +.model npn NPN( Vtf=4 Cjc=3.638p Nc=2 Tr=239.5n Ne=1.259 ++ Cje=4.493p Isc=0 Xtb=1.5 Rb=10 Rc=1 ++ Tf=301.2p Xti=3 Ikr=0 Bf=416.4 Fc=.5 ++ Ise=6.734f Br=.7371 Ikf=66.78m Mje=.2593 Mjc=.3085 ++ Vaf=74.03 Vjc=.75 Vje=.75 Xtf=2 Itf=.4 ++ Is=6.734f Eg=1.11 ) |