diff options
Diffstat (limited to 'include/bedbug')
| -rwxr-xr-x | include/bedbug/bedbug.h | 42 | ||||
| -rwxr-xr-x | include/bedbug/ppc.h | 413 | ||||
| -rwxr-xr-x | include/bedbug/regs.h | 403 | ||||
| -rwxr-xr-x | include/bedbug/tables.h | 601 | ||||
| -rwxr-xr-x | include/bedbug/type.h | 26 |
5 files changed, 1485 insertions, 0 deletions
diff --git a/include/bedbug/bedbug.h b/include/bedbug/bedbug.h new file mode 100755 index 0000000..471215e --- /dev/null +++ b/include/bedbug/bedbug.h @@ -0,0 +1,42 @@ +/* $Id$ */ + +#ifndef _BEDBUG_H +#define _BEDBUG_H + +#ifndef NULL +#define NULL 0 +#endif + +#define _USE_PROTOTYPES + +#ifndef isblank +#define isblank(c) isspace((int)(c)) +#endif + +#ifndef __P +#if defined(_USE_PROTOTYPES) && (defined(__STDC__) || defined(__cplusplus)) +#define __P(protos) protos /* full-blown ANSI C */ +#else +#define __P(protos) () /* traditional C preprocessor */ +#endif +#endif + +#define assert( condition ) if( (condition) ) _exit(0) + +#endif /* _BEDBUG_H */ + + +/* + * Copyright (c) 2001 William L. Pitts + * All rights reserved. + * + * Redistribution and use in source and binary forms are freely + * permitted provided that the above copyright notice and this + * paragraph and the following disclaimer are duplicated in all + * such forms. + * + * This software is provided "AS IS" and without any express or + * implied warranties, including, without limitation, the implied + * warranties of merchantability and fitness for a particular + * purpose. + */ diff --git a/include/bedbug/ppc.h b/include/bedbug/ppc.h new file mode 100755 index 0000000..9cc8f9f --- /dev/null +++ b/include/bedbug/ppc.h @@ -0,0 +1,413 @@ +/* $Id$ */ + +#ifndef _PPC_H +#define _PPC_H + +/*====================================================================== + * + * OPERANDS + * + *======================================================================*/ + +enum OP_FIELD { + O_AA = 1, O_BD, O_BI, O_BO, O_crbD, O_crbA, O_crbB, O_CRM, O_d, O_frC, O_frD, + O_frS, O_IMM, O_LI, O_LK, O_MB, O_ME, O_NB, O_OE, O_rA, O_rB, O_Rc, O_rD, + O_rS, O_SH, O_SIMM, O_SR, O_TO, O_UIMM, O_crfD, O_crfS, O_L, O_spr, O_tbr, + O_cr2 }; + +struct operand { + enum OP_FIELD field; /* The operand identifier from the + enum above */ + + char * name; /* Symbolic name of this operand */ + + unsigned int bits; /* The number of bits used by this + operand */ + + unsigned int shift; /* How far to the right the operand + should be shifted so that it is + aligned at the beginning of the + word */ + + unsigned int hint; /* A bitwise-inclusive-OR of the + values shown below. These are used + tell the disassembler how to print + this operand */ +}; + +/* Values for operand hint */ +#define OH_SILENT 0x01 /* dont print this operand */ +#define OH_ADDR 0x02 /* this operand is an address */ +#define OH_REG 0x04 /* this operand is a register */ +#define OH_SPR 0x08 /* this operand is an SPR */ +#define OH_TBR 0x10 /* this operand is a TBR */ +#define OH_OFFSET 0x20 /* this operand is an offset */ +#define OH_LITERAL 0x40 /* a literal string */ + + +/*====================================================================== + * + * OPCODES + * + *======================================================================*/ + +/* From the MPCxxx instruction set documentation, all instructions are + * 32 bits long and word aligned. Bits 0-5 always specify the primary + * opcode. Many instructions also have an extended opcode. + */ + +#define GET_OPCD(i) (((unsigned long)(i) >> 26) & 0x3f) +#define MAKE_OPCODE(i) ((((unsigned long)(i)) & 0x3f) << 26) + +/* The MPC860 User's Manual, Appendix D.4 contains the definitions of the + * instruction forms + */ + + +/*------------------------------------------------- + * I-Form Instructions: + * bX + *------------------------------------------------- + * OPCD | LI |AA|LK + *-------------------------------------------------*/ + +#define I_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1)) +#define I_MASK I_OPCODE(0x3f,0x1,0x1) + + +/*------------------------------------------------- + * B-Form Instructions: + * bcX + *------------------------------------------------- + * OPCD | BO | BI | BD |AA|LK + *-------------------------------------------------*/ + +#define B_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1)) +#define B_MASK B_OPCODE(0x3f,0x1,0x1) + + +/*------------------------------------------------- + * SC-Form Instructions: + * sc + *------------------------------------------------- + * OPCD | 00000 | 00000 | 00000000000000 |1|0 + *-------------------------------------------------*/ + +#define SC_OPCODE(i) (MAKE_OPCODE(i) | 0x2) +#define SC_MASK SC_OPCODE(0x3f) + + +/*------------------------------------------------- + * D-Form Instructions: + * addi addic addic. addis andi. andis. cmpi cmpli + * lbz lbzu lha lhau lhz lhzu lmw lwz lwzu mulli + * ori oris stb stbu sth sthu stmw stw stwu subfic + * twi xori xoris + *------------------------------------------------- + * OPCD | D | A | d + * OPCD | D | A | SIMM + * OPCD | S | A | d + * OPCD | S | A | UIMM + * OPCD |crfD|0|L| A | SIMM + * OPCD |crfD|0|L| A | UIMM + * OPCD | TO | A | SIMM + *-------------------------------------------------*/ + +#define D_OPCODE(i) MAKE_OPCODE(i) +#define D_MASK MAKE_OPCODE(0x3f) + + +/*------------------------------------------------- + * DS-Form Instructions: + * (none supported by MPC860) + *------------------------------------------------- + * OPCD | D | A | ds |XO + * OPCD | S | A | ds |XO + *-------------------------------------------------*/ + +#define DS_OPCODE(i,xo) (MAKE_OPCODE(i) | ((xo) & 0x3)) +#define DS_MASK DS_OPCODE(0x3f,0x1) + + +/*--------------------------------------------------- + * X-Form Instructions: + * andX andcX cmp cmpl cntlzwX dcbf dcbi dcbst dcbt + * dcbtst dcbz eciwx ecowx eieio eqvX extsbX extshX + * icbi lbzux lbxz lhaux lhax lhbrx lhzux lhxz lswi + * lswx lwarx lwbrx lwzux lwxz mcrfs mcrxr mfcr + * mfmsr mfsr mfsrin mtmsr mtsr mtsrin nandX norX + * orX orcX slwX srawX srawiX srwX stbux stbx + * sthbrx sthuxsthx stswi stswx stwbrx stwcx. stwux + * stwx sync tlbie tlbld tlbli tlbsync tw xorX + *--------------------------------------------------- + * OPCD | D | A | B | XO |0 + * OPCD | D | A | NB | XO |0 + * OPCD | D | 00000 | B | XO |0 + * OPCD | D | 00000 | 00000 | XO |0 + * OPCD | D |0| SR | 00000 | XO |0 + * OPCD | S | A | B | XO |Rc + * OPCD | S | A | B | XO |1 + * OPCD | S | A | B | XO |0 + * OPCD | S | A | NB | XO |0 + * OPCD | S | A | 00000 | XO |Rc + * OPCD | S | 00000 | B | XO |0 + * OPCD | S | 00000 | 00000 | XO |0 + * OPCD | S |0| SR | 00000 | XO |0 + * OPCD | S | A | SH | XO |Rc + * OPCD |crfD|0|L| A | SH | XO |0 + * OPCD |crfD |00| A | B | XO |0 + * OPCD |crfD |00|crfS |00| 00000 | XO |0 + * OPCD |crfD |00| 00000 | 00000 | XO |0 + * OPCD |crfD |00| 00000 | IMM |0| XO |Rc + * OPCD | TO | A | B | XO |0 + * OPCD | D | 00000 | B | XO |Rc + * OPCD | D | 00000 | 00000 | XO |Rc + * OPCD | crbD | 00000 | 00000 | XO |Rc + * OPCD | 00000 | A | B | XO |0 + * OPCD | 00000 | 00000 | B | XO |0 + * OPCD | 00000 | 00000 | 00000 | XO |0 + *---------------------------------------------------*/ + +#define X_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \ + ((rc) & 0x1)) +#define X_MASK X_OPCODE(0x3f,0x3ff,0x1) + + +/*--------------------------------------------------- + * XL-Form Instructions: + * bcctrX bclrX crand crandc creqv crnand crnor cror + * croc crxorisync mcrf rfi + *--------------------------------------------------- + * OPCD | BO | BI | 00000 | XO |LK + * OPCD | crbD | crbA | crbB | XO |0 + * OPCD |crfD |00|crfS |00| 00000 | XO |0 + * OPCD | 00000 | 00000 | 00000 | XO |0 + *---------------------------------------------------*/ + +#define XL_OPCODE(i,xo,lk) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \ + ((lk) & 0x1)) +#define XL_MASK XL_OPCODE(0x3f,0x3ff,0x1) + + +/*--------------------------------------------------- + * XFX-Form Instructions: + * mfspr mftb mtcrf mtspr + *--------------------------------------------------- + * OPCD | D | spr | XO |0 + * OPCD | D |0| CRM |0| XO |0 + * OPCD | S | spr | XO |0 + * OPCD | D | tbr | XO |0 + *---------------------------------------------------*/ + +#define XFX_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \ + ((rc) & 0x1)) +#define XFX_MASK XFX_OPCODE(0x3f,0x3ff,0x1) + + +/*--------------------------------------------------- + * XFL-Form Instructions: + * (none supported by MPC860) + *--------------------------------------------------- + * OPCD |0| FM |0| B | XO |0 + *---------------------------------------------------*/ + +#define XFL_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \ + ((rc) & 0x1)) +#define XFL_MASK XFL_OPCODE(0x3f,0x3ff,0x1) + + +/*--------------------------------------------------- + * XS-Form Instructions: + * (none supported by MPC860) + *--------------------------------------------------- + * OPCD | S | A | sh | XO |sh|LK + *---------------------------------------------------*/ + +#define XS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1ff) << 2) | \ + ((rc) & 0x1)) +#define XS_MASK XS_OPCODE(0x3f,0x1ff,0x1) + + +/*--------------------------------------------------- + * XO-Form Instructions: + * addX addcXaddeX addmeX addzeX divwX divwuX mulhwX + * mulhwuX mullwX negX subfX subfcX subfeX subfmeX + * subfzeX + *--------------------------------------------------- + * OPCD | D | A | B |OE| XO |Rc + * OPCD | D | A | B |0 | XO |Rc + * OPCD | D | A | 00000 |OE| XO |Rc + *---------------------------------------------------*/ + +#define XO_OPCODE(i,xo,oe,rc) (MAKE_OPCODE(i) | (((oe) & 0x1) << 10) | \ + (((xo) & 0x1ff) << 1) | ((rc) & 0x1)) +#define XO_MASK XO_OPCODE(0x3f,0x1ff,0x1,0x1) + + +/*--------------------------------------------------- + * A-Form Instructions: + * (none supported by MPC860) + *--------------------------------------------------- + * OPCD | D | A | B |00000| XO |Rc + * OPCD | D | A | B | C | XO |Rc + * OPCD | D | A | 00000 | C | XO |Rc + * OPCD | D | 00000 | B |00000| XO |Rc + *---------------------------------------------------*/ + +#define A_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1f) << 1) | \ + ((rc) & 0x1)) +#define A_MASK A_OPCODE(0x3f,0x1f,0x1) + + +/*--------------------------------------------------- + * M-Form Instructions: + * rlwimiX rlwinmX rlwnmX + *--------------------------------------------------- + * OPCD | S | A | SH | MB | ME |Rc + * OPCD | S | A | B | MB | ME |Rc + *---------------------------------------------------*/ + +#define M_OPCODE(i,rc) (MAKE_OPCODE(i) | ((rc) & 0x1)) +#define M_MASK M_OPCODE(0x3f,0x1) + + +/*--------------------------------------------------- + * MD-Form Instructions: + * (none supported by MPC860) + *--------------------------------------------------- + * OPCD | S | A | sh | mb | XO |sh|Rc + * OPCD | S | A | sh | me | XO |sh|Rc + *---------------------------------------------------*/ + +#define MD_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x7) << 2) | \ + ((rc) & 0x1)) +#define MD_MASK MD_OPCODE(0x3f,0x7,0x1) + + +/*--------------------------------------------------- + * MDS-Form Instructions: + * (none supported by MPC860) + *--------------------------------------------------- + * OPCD | S | A | B | mb | XO |Rc + * OPCD | S | A | B | me | XO |Rc + *---------------------------------------------------*/ + +#define MDS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0xf) << 1) | \ + ((rc) & 0x1)) +#define MDS_MASK MDS_OPCODE(0x3f,0xf,0x1) + +#ifndef FALSE +#define FALSE 0 +#define TRUE (!FALSE) +#endif + +#define INSTRUCTION( memaddr ) ntohl(*(unsigned long *)(memaddr)) + +#define MAX_OPERANDS 8 + +struct ppc_ctx; + +struct opcode { + unsigned long opcode; /* The complete opcode as produced by + one of the XXX_OPCODE macros above */ + + unsigned long mask; /* The mask to use on an instruction + before comparing with the opcode + field to see if it matches */ + + enum OP_FIELD fields[MAX_OPERANDS]; + /* An array defining the operands for + this opcode. The values of the + array are the operand identifiers */ + + int (*hfunc)(struct ppc_ctx *); + /* Address of a function to handle the given + mnemonic */ + + char * name; /* The symbolic name of this opcode */ + + unsigned int hint; /* A bitwise-inclusive-OR of the + values shown below. These are used + tell the disassembler how to print + some operands for this opcode */ +}; + +/* values for opcode hints */ +#define H_RELATIVE 0x1 /* The address operand is relative */ +#define H_IMM_HIGH 0x2 /* [U|S]IMM field shifted high */ +#define H_RA0_IS_0 0x4 /* If rA = 0 then treat as literal 0 */ + +struct ppc_ctx { + struct opcode * op; + unsigned long instr; + unsigned int flags; + int datalen; + char data[ 256 ]; + char radix_fmt[ 8 ]; + unsigned char * virtual; +}; + + +/*====================================================================== + * + * FUNCTIONS + * + *======================================================================*/ + +/* Values for flags as passed to various ppc routines */ +#define F_RADOCTAL 0x1 /* output radix = unsigned octal */ +#define F_RADUDECIMAL 0x2 /* output radix = unsigned decimal */ +#define F_RADSDECIMAL 0x4 /* output radix = signed decimal */ +#define F_RADHEX 0x8 /* output radix = unsigned hex */ +#define F_SIMPLE 0x10 /* use simplified mnemonics */ +#define F_SYMBOL 0x20 /* use symbol lookups for addresses */ +#define F_INSTR 0x40 /* output the raw instruction */ +#define F_LOCALMEM 0x80 /* retrieve opcodes from local memory + rather than from the HMI */ +#define F_LINENO 0x100 /* show line number info if available */ +#define F_VALIDONLY 0x200 /* cache: valid entries only */ + +/* Values for assembler error codes */ +#define E_ASM_BAD_OPCODE 1 +#define E_ASM_NUM_OPERANDS 2 +#define E_ASM_BAD_REGISTER 3 +#define E_ASM_BAD_SPR 4 +#define E_ASM_BAD_TBR 5 + +extern int disppc __P((unsigned char *,unsigned char *,int, + int (*)(const char *), unsigned long)); +extern int print_source_line __P((char *,char *,int, + int (*pfunc)(const char *))); +extern int find_next_address __P((unsigned char *,int,struct pt_regs *)); +extern int handle_bc __P((struct ppc_ctx *)); +extern unsigned long asmppc __P((unsigned long,char*,int*)); +extern char *asm_error_str __P((int)); + +/*====================================================================== + * + * GLOBAL VARIABLES + * + *======================================================================*/ + +extern struct operand operands[]; +extern const unsigned int n_operands; +extern struct opcode opcodes[]; +extern const unsigned int n_opcodes; + +#endif /* _PPC_H */ + + +/* + * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks + * All rights reserved. + * + * Redistribution and use in source and binary forms are freely + * permitted provided that the above copyright notice and this + * paragraph and the following disclaimer are duplicated in all + * such forms. + * + * This software is provided "AS IS" and without any express or + * implied warranties, including, without limitation, the implied + * warranties of merchantability and fitness for a particular + * purpose. + */ diff --git a/include/bedbug/regs.h b/include/bedbug/regs.h new file mode 100755 index 0000000..938e435 --- /dev/null +++ b/include/bedbug/regs.h @@ -0,0 +1,403 @@ +/* $Id$ */ + +#ifndef _REGS_H +#define _REGS_H + +/* Special Purpose Registers */ + +#define SPR_CR -1 +#define SPR_MSR -2 + +#define SPR_XER 1 +#define SPR_LR 8 +#define SPR_CTR 9 +#define SPR_DSISR 18 +#define SPR_DAR 19 +#define SPR_DEC 22 +#define SPR_SRR0 26 +#define SPR_SRR1 27 +#define SPR_EIE 80 +#define SPR_EID 81 +#define SPR_CMPA 144 +#define SPR_CMPB 145 +#define SPR_CMPC 146 +#define SPR_CMPD 147 +#define SPR_ICR 148 +#define SPR_DER 149 +#define SPR_COUNTA 150 +#define SPR_COUNTB 151 +#define SPR_CMPE 152 +#define SPR_CMPF 153 +#define SPR_CMPG 154 +#define SPR_CMPH 155 +#define SPR_LCTRL1 156 +#define SPR_LCTRL2 157 +#define SPR_ICTRL 158 +#define SPR_BAR 159 +#define SPR_USPRG0 256 +#define SPR_SPRG4_RO 260 +#define SPR_SPRG5_RO 261 +#define SPR_SPRG6_RO 262 +#define SPR_SPRG7_RO 263 +#define SPR_SPRG0 272 +#define SPR_SPRG1 273 +#define SPR_SPRG2 274 +#define SPR_SPRG3 275 +#define SPR_SPRG4 276 +#define SPR_SPRG5 277 +#define SPR_SPRG6 278 +#define SPR_SPRG7 279 +#define SPR_EAR 282 /* MPC603e core */ +#define SPR_TBL 284 +#define SPR_TBU 285 +#define SPR_PVR 287 +#define SPR_IC_CST 560 +#define SPR_IC_ADR 561 +#define SPR_IC_DAT 562 +#define SPR_DC_CST 568 +#define SPR_DC_ADR 569 +#define SPR_DC_DAT 570 +#define SPR_DPDR 630 +#define SPR_IMMR 638 +#define SPR_MI_CTR 784 +#define SPR_MI_AP 786 +#define SPR_MI_EPN 787 +#define SPR_MI_TWC 789 +#define SPR_MI_RPN 790 +#define SPR_MD_CTR 792 +#define SPR_M_CASID 793 +#define SPR_MD_AP 794 +#define SPR_MD_EPN 795 +#define SPR_M_TWB 796 +#define SPR_MD_TWC 797 +#define SPR_MD_RPN 798 +#define SPR_M_TW 799 +#define SPR_MI_DBCAM 816 +#define SPR_MI_DBRAM0 817 +#define SPR_MI_DBRAM1 818 +#define SPR_MD_DBCAM 824 +#define SPR_MD_DBRAM0 825 +#define SPR_MD_DBRAM1 826 +#define SPR_ZPR 944 +#define SPR_PID 945 +#define SPR_CCR0 947 +#define SPR_IAC3 948 +#define SPR_IAC4 949 +#define SPR_DVC1 950 +#define SPR_DVC2 951 +#define SPR_SGR 953 +#define SPR_DCWR 954 +#define SPR_SLER 955 +#define SPR_SU0R 956 +#define SPR_DBCR1 957 +#define SPR_ICDBDR 979 +#define SPR_ESR 980 +#define SPR_DEAR 981 +#define SPR_EVPR 982 +#define SPR_TSR 984 +#define SPR_TCR 986 +#define SPR_PIT 987 +#define SPR_SRR2 990 +#define SPR_SRR3 991 +#define SPR_DBSR 1008 +#define SPR_DBCR0 1010 +#define SPR_IABR 1010 /* MPC603e core */ +#define SPR_IAC1 1012 +#define SPR_IAC2 1013 +#define SPR_DAC1 1014 +#define SPR_DAC2 1015 +#define SPR_DCCR 1018 +#define SPR_ICCR 1019 + +/* Bits for the DBCR0 register */ +#define DBCR0_EDM 0x80000000 +#define DBCR0_IDM 0x40000000 +#define DBCR0_RST 0x30000000 +#define DBCR0_IC 0x08000000 +#define DBCR0_BT 0x04000000 +#define DBCR0_EDE 0x02000000 +#define DBCR0_TDE 0x01000000 +#define DBCR0_IA1 0x00800000 +#define DBCR0_IA2 0x00400000 +#define DBCR0_IA12 0x00200000 +#define DBCR0_IA12X 0x00100000 +#define DBCR0_IA3 0x00080000 +#define DBCR0_IA4 0x00040000 +#define DBCR0_IA34 0x00020000 +#define DBCR0_IA34X 0x00010000 +#define DBCR0_IA12T 0x00008000 +#define DBCR0_IA34T 0x00004000 +#define DBCR0_FT 0x00000001 + +/* Bits for the DBCR1 register */ +#define DBCR1_D1R 0x80000000 +#define DBCR1_D2R 0x40000000 +#define DBCR1_D1W 0x20000000 +#define DBCR1_D2W 0x10000000 +#define DBCR1_D1S 0x0C000000 +#define DBCR1_D2S 0x03000000 +#define DBCR1_DA12 0x00800000 +#define DBCR1_DA12X 0x00400000 +#define DBCR1_DV1M 0x000C0000 +#define DBCR1_DV2M 0x00030000 +#define DBCR1_DV1BE 0x0000F000 +#define DBCR1_DV2BE 0x00000F00 + +/* Bits for the DBSR register */ +#define DBSR_IC 0x80000000 +#define DBSR_BT 0x40000000 +#define DBSR_EDE 0x20000000 +#define DBSR_TIE 0x10000000 +#define DBSR_UDE 0x08000000 +#define DBSR_IA1 0x04000000 +#define DBSR_IA2 0x02000000 +#define DBSR_DR1 0x01000000 +#define DBSR_DW1 0x00800000 +#define DBSR_DR2 0x00400000 +#define DBSR_DW2 0x00200000 +#define DBSR_IDE 0x00100000 +#define DBSR_IA3 0x00080000 +#define DBSR_IA4 0x00040000 +#define DBSR_MRR 0x00000300 + +struct spr_info { + int spr_val; + char spr_name[ 10 ]; +}; + +extern struct spr_info spr_map[]; +extern const unsigned int n_sprs; + + +#define SET_REGISTER( str, val ) \ +({ unsigned long __value = (val); \ + asm volatile( str : : "r" (__value)); \ + __value; }) + +#define GET_REGISTER( str ) \ +({ unsigned long __value; \ + asm volatile( str : "=r" (__value) : ); \ + __value; }) + +#define GET_CR() GET_REGISTER( "mfcr %0" ) +#define SET_CR(val) SET_REGISTER( "mtcr %0", val ) +#define GET_MSR() GET_REGISTER( "mfmsr %0" ) +#define SET_MSR(val) SET_REGISTER( "mtmsr %0", val ) +#define GET_XER() GET_REGISTER( "mfspr %0,1" ) +#define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val ) +#define GET_LR() GET_REGISTER( "mfspr %0,8" ) +#define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val ) +#define GET_CTR() GET_REGISTER( "mfspr %0,9" ) +#define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val ) +#define GET_DSISR() GET_REGISTER( "mfspr %0,18" ) +#define SET_DSISR(val) SET_REGISTER( "mtspr 18,%0", val ) +#define GET_DAR() GET_REGISTER( "mfspr %0,19" ) +#define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val ) +#define GET_DEC() GET_REGISTER( "mfspr %0,22" ) +#define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val ) +#define GET_SRR0() GET_REGISTER( "mfspr %0,26" ) +#define SET_SRR0(val) SET_REGISTER( "mtspr 26,%0", val ) +#define GET_SRR1() GET_REGISTER( "mfspr %0,27" ) +#define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val ) +#define GET_EIE() GET_REGISTER( "mfspr %0,80" ) +#define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val ) +#define GET_EID() GET_REGISTER( "mfspr %0,81" ) +#define SET_EID(val) SET_REGISTER( "mtspr 81,%0", val ) +#define GET_CMPA() GET_REGISTER( "mfspr %0,144" ) +#define SET_CMPA(val) SET_REGISTER( "mtspr 144,%0", val ) +#define GET_CMPB() GET_REGISTER( "mfspr %0,145" ) +#define SET_CMPB(val) SET_REGISTER( "mtspr 145,%0", val ) +#define GET_CMPC() GET_REGISTER( "mfspr %0,146" ) +#define SET_CMPC(val) SET_REGISTER( "mtspr 146,%0", val ) +#define GET_CMPD() GET_REGISTER( "mfspr %0,147" ) +#define SET_CMPD(val) SET_REGISTER( "mtspr 147,%0", val ) +#define GET_ICR() GET_REGISTER( "mfspr %0,148" ) +#define SET_ICR(val) SET_REGISTER( "mtspr 148,%0", val ) +#define GET_DER() GET_REGISTER( "mfspr %0,149" ) +#define SET_DER(val) SET_REGISTER( "mtspr 149,%0", val ) +#define GET_COUNTA() GET_REGISTER( "mfspr %0,150" ) +#define SET_COUNTA(val) SET_REGISTER( "mtspr 150,%0", val ) +#define GET_COUNTB() GET_REGISTER( "mfspr %0,151" ) +#define SET_COUNTB(val) SET_REGISTER( "mtspr 151,%0", val ) +#define GET_CMPE() GET_REGISTER( "mfspr %0,152" ) +#define SET_CMPE(val) SET_REGISTER( "mtspr 152,%0", val ) +#define GET_CMPF() GET_REGISTER( "mfspr %0,153" ) +#define SET_CMPF(val) SET_REGISTER( "mtspr 153,%0", val ) +#define GET_CMPG() GET_REGISTER( "mfspr %0,154" ) +#define SET_CMPG(val) SET_REGISTER( "mtspr 154,%0", val ) +#define GET_CMPH() GET_REGISTER( "mfspr %0,155" ) +#define SET_CMPH(val) SET_REGISTER( "mtspr 155,%0", val ) +#define GET_LCTRL1() GET_REGISTER( "mfspr %0,156" ) +#define SET_LCTRL1(val) SET_REGISTER( "mtspr 156,%0", val ) +#define GET_LCTRL2() GET_REGISTER( "mfspr %0,157" ) +#define SET_LCTRL2(val) SET_REGISTER( "mtspr 157,%0", val ) +#define GET_ICTRL() GET_REGISTER( "mfspr %0,158" ) +#define SET_ICTRL(val) SET_REGISTER( "mtspr 158,%0", val ) +#define GET_BAR() GET_REGISTER( "mfspr %0,159" ) +#define SET_BAR(val) SET_REGISTER( "mtspr 159,%0", val ) +#define GET_USPRG0() GET_REGISTER( "mfspr %0,256" ) +#define SET_USPRG0(val) SET_REGISTER( "mtspr 256,%0", val ) +#define GET_SPRG4_RO() GET_REGISTER( "mfspr %0,260" ) +#define SET_SPRG4_RO(val) SET_REGISTER( "mtspr 260,%0", val ) +#define GET_SPRG5_RO() GET_REGISTER( "mfspr %0,261" ) +#define SET_SPRG5_RO(val) SET_REGISTER( "mtspr 261,%0", val ) +#define GET_SPRG6_RO() GET_REGISTER( "mfspr %0,262" ) +#define SET_SPRG6_RO(val) SET_REGISTER( "mtspr 262,%0", val ) +#define GET_SPRG7_RO() GET_REGISTER( "mfspr %0,263" ) +#define SET_SPRG7_RO(val) SET_REGISTER( "mtspr 263,%0", val ) +#define GET_SPRG0() GET_REGISTER( "mfspr %0,272" ) +#define SET_SPRG0(val) SET_REGISTER( "mtspr 272,%0", val ) +#define GET_SPRG1() GET_REGISTER( "mfspr %0,273" ) +#define SET_SPRG1(val) SET_REGISTER( "mtspr 273,%0", val ) +#define GET_SPRG2() GET_REGISTER( "mfspr %0,274" ) +#define SET_SPRG2(val) SET_REGISTER( "mtspr 274,%0", val ) +#define GET_SPRG3() GET_REGISTER( "mfspr %0,275" ) +#define SET_SPRG3(val) SET_REGISTER( "mtspr 275,%0", val ) +#define GET_SPRG4() GET_REGISTER( "mfspr %0,276" ) +#define SET_SPRG4(val) SET_REGISTER( "mtspr 276,%0", val ) +#define GET_SPRG5() GET_REGISTER( "mfspr %0,277" ) +#define SET_SPRG5(val) SET_REGISTER( "mtspr 277,%0", val ) +#define GET_SPRG6() GET_REGISTER( "mfspr %0,278" ) +#define SET_SPRG6(val) SET_REGISTER( "mtspr 278,%0", val ) +#define GET_SPRG7() GET_REGISTER( "mfspr %0,279" ) +#define SET_SPRG7(val) SET_REGISTER( "mtspr 279,%0", val ) +#define GET_EAR() GET_REGISTER( "mfspr %0,282" ) +#define SET_EAR(val) SET_REGISTER( "mtspr 282,%0", val ) +#define GET_TBL() GET_REGISTER( "mfspr %0,284" ) +#define SET_TBL(val) SET_REGISTER( "mtspr 284,%0", val ) +#define GET_TBU() GET_REGISTER( "mfspr %0,285" ) +#define SET_TBU(val) SET_REGISTER( "mtspr 285,%0", val ) +#define GET_PVR() GET_REGISTER( "mfspr %0,287" ) +#define SET_PVR(val) SET_REGISTER( "mtspr 287,%0", val ) +#define GET_IC_CST() GET_REGISTER( "mfspr %0,560" ) +#define SET_IC_CST(val) SET_REGISTER( "mtspr 560,%0", val ) +#define GET_IC_ADR() GET_REGISTER( "mfspr %0,561" ) +#define SET_IC_ADR(val) SET_REGISTER( "mtspr 561,%0", val ) +#define GET_IC_DAT() GET_REGISTER( "mfspr %0,562" ) +#define SET_IC_DAT(val) SET_REGISTER( "mtspr 562,%0", val ) +#define GET_DC_CST() GET_REGISTER( "mfspr %0,568" ) +#define SET_DC_CST(val) SET_REGISTER( "mtspr 568,%0", val ) +#define GET_DC_ADR() GET_REGISTER( "mfspr %0,569" ) +#define SET_DC_ADR(val) SET_REGISTER( "mtspr 569,%0", val ) +#define GET_DC_DAT() GET_REGISTER( "mfspr %0,570" ) +#define SET_DC_DAT(val) SET_REGISTER( "mtspr 570,%0", val ) +#define GET_DPDR() GET_REGISTER( "mfspr %0,630" ) +#define SET_DPDR(val) SET_REGISTER( "mtspr 630,%0", val ) +#define GET_IMMR() GET_REGISTER( "mfspr %0,638" ) +#define SET_IMMR(val) SET_REGISTER( "mtspr 638,%0", val ) +#define GET_MI_CTR() GET_REGISTER( "mfspr %0,784" ) +#define SET_MI_CTR(val) SET_REGISTER( "mtspr 784,%0", val ) +#define GET_MI_AP() GET_REGISTER( "mfspr %0,786" ) +#define SET_MI_AP(val) SET_REGISTER( "mtspr 786,%0", val ) +#define GET_MI_EPN() GET_REGISTER( "mfspr %0,787" ) +#define SET_MI_EPN(val) SET_REGISTER( "mtspr 787,%0", val ) +#define GET_MI_TWC() GET_REGISTER( "mfspr %0,789" ) +#define SET_MI_TWC(val) SET_REGISTER( "mtspr 789,%0", val ) +#define GET_MI_RPN() GET_REGISTER( "mfspr %0,790" ) +#define SET_MI_RPN(val) SET_REGISTER( "mtspr 790,%0", val ) +#define GET_MD_CTR() GET_REGISTER( "mfspr %0,792" ) +#define SET_MD_CTR(val) SET_REGISTER( "mtspr 792,%0", val ) +#define GET_M_CASID() GET_REGISTER( "mfspr %0,793" ) +#define SET_M_CASID(val) SET_REGISTER( "mtspr 793,%0", val ) +#define GET_MD_AP() GET_REGISTER( "mfspr %0,794" ) +#define SET_MD_AP(val) SET_REGISTER( "mtspr ,794%0", val ) +#define GET_MD_EPN() GET_REGISTER( "mfspr %0,795" ) +#define SET_MD_EPN(val) SET_REGISTER( "mtspr 795,%0", val ) +#define GET_M_TWB() GET_REGISTER( "mfspr %0,796" ) +#define SET_M_TWB(val) SET_REGISTER( "mtspr 796,%0", val ) +#define GET_MD_TWC() GET_REGISTER( "mfspr %0,797" ) +#define SET_MD_TWC(val) SET_REGISTER( "mtspr 797,%0", val ) +#define GET_MD_RPN() GET_REGISTER( "mfspr %0,798" ) +#define SET_MD_RPN(val) SET_REGISTER( "mtspr 798,%0", val ) +#define GET_M_TW() GET_REGISTER( "mfspr %0,799" ) +#define SET_M_TW(val) SET_REGISTER( "mtspr 799,%0", val ) +#define GET_MI_DBCAM() GET_REGISTER( "mfspr %0,816" ) +#define SET_MI_DBCAM(val) SET_REGISTER( "mtspr 816,%0", val ) +#define GET_MI_DBRAM0() GET_REGISTER( "mfspr %0,817" ) +#define SET_MI_DBRAM0(val) SET_REGISTER( "mtspr 817,%0", val ) +#define GET_MI_DBRAM1() GET_REGISTER( "mfspr %0,818" ) +#define SET_MI_DBRAM1(val) SET_REGISTER( "mtspr 818,%0", val ) +#define GET_MD_DBCAM() GET_REGISTER( "mfspr %0,824" ) +#define SET_MD_DBCA(val) SET_REGISTER( "mtspr 824,%0", val ) +#define GET_MD_DBRAM0() GET_REGISTER( "mfspr %0,825" ) +#define SET_MD_DBRAM0(val) SET_REGISTER( "mtspr 825,%0", val ) +#define GET_MD_DBRAM1() GET_REGISTER( "mfspr %0,826" ) +#define SET_MD_DBRAM1(val) SET_REGISTER( "mtspr 826,%0", val ) +#define GET_ZPR() GET_REGISTER( "mfspr %0,944" ) +#define SET_ZPR(val) SET_REGISTER( "mtspr 944,%0", val ) +#define GET_PID() GET_REGISTER( "mfspr %0,945" ) +#define SET_PID(val) SET_REGISTER( "mtspr 945,%0", val ) +#define GET_CCR0() GET_REGISTER( "mfspr %0,947" ) +#define SET_CCR0(val) SET_REGISTER( "mtspr 947,%0", val ) +#define GET_IAC3() GET_REGISTER( "mfspr %0,948" ) +#define SET_IAC3(val) SET_REGISTER( "mtspr 948,%0", val ) +#define GET_IAC4() GET_REGISTER( "mfspr %0,949" ) +#define SET_IAC4(val) SET_REGISTER( "mtspr 949,%0", val ) +#define GET_DVC1() GET_REGISTER( "mfspr %0,950" ) +#define SET_DVC1(val) SET_REGISTER( "mtspr 950,%0", val ) +#define GET_DVC2() GET_REGISTER( "mfspr %0,951" ) +#define SET_DVC2(val) SET_REGISTER( "mtspr 951,%0", val ) +#define GET_SGR() GET_REGISTER( "mfspr %0,953" ) +#define SET_SGR(val) SET_REGISTER( "mtspr 953,%0", val ) +#define GET_DCWR() GET_REGISTER( "mfspr %0,954" ) +#define SET_DCWR(val) SET_REGISTER( "mtspr 954,%0", val ) +#define GET_SLER() GET_REGISTER( "mfspr %0,955" ) +#define SET_SLER(val) SET_REGISTER( "mtspr 955,%0", val ) +#define GET_SU0R() GET_REGISTER( "mfspr %0,956" ) +#define SET_SU0R(val) SET_REGISTER( "mtspr 956,%0", val ) +#define GET_DBCR1() GET_REGISTER( "mfspr %0,957" ) +#define SET_DBCR1(val) SET_REGISTER( "mtspr 957,%0", val ) +#define GET_ICDBDR() GET_REGISTER( "mfspr %0,979" ) +#define SET_ICDBDR(val) SET_REGISTER( "mtspr 979,%0", val ) +#define GET_ESR() GET_REGISTER( "mfspr %0,980" ) +#define SET_ESR(val) SET_REGISTER( "mtspr 980,%0", val ) +#define GET_DEAR() GET_REGISTER( "mfspr %0,981" ) +#define SET_DEAR(val) SET_REGISTER( "mtspr 981,%0", val ) +#define GET_EVPR() GET_REGISTER( "mfspr %0,982" ) +#define SET_EVPR(val) SET_REGISTER( "mtspr 982,%0", val ) +#define GET_TSR() GET_REGISTER( "mfspr %0,984" ) +#define SET_TSR(val) SET_REGISTER( "mtspr 984,%0", val ) +#define GET_TCR() GET_REGISTER( "mfspr %0,986" ) +#define SET_TCR(val) SET_REGISTER( "mtspr 986,%0", val ) +#define GET_PIT() GET_REGISTER( "mfspr %0,987" ) +#define SET_PIT(val) SET_REGISTER( "mtspr 987,%0", val ) +#define GET_SRR2() GET_REGISTER( "mfspr %0,990" ) +#define SET_SRR2(val) SET_REGISTER( "mtspr 990,%0", val ) +#define GET_SRR3() GET_REGISTER( "mfspr %0,991" ) +#define SET_SRR3(val) SET_REGISTER( "mtspr 991,%0", val ) +#define GET_DBSR() GET_REGISTER( "mfspr %0,1008" ) +#define SET_DBSR(val) SET_REGISTER( "mtspr 1008,%0", val ) +#define GET_DBCR0() GET_REGISTER( "mfspr %0,1010" ) +#define SET_DBCR0(val) SET_REGISTER( "mtspr 1010,%0", val ) +#define GET_IABR() GET_REGISTER( "mfspr %0,1010" ) +#define SET_IABR(val) SET_REGISTER( "mtspr 1010,%0", val ) +#define GET_IAC1() GET_REGISTER( "mfspr %0,1012" ) +#define SET_IAC1(val) SET_REGISTER( "mtspr 1012,%0", val ) +#define GET_IAC2() GET_REGISTER( "mfspr %0,1013" ) +#define SET_IAC2(val) SET_REGISTER( "mtspr 1013,%0", val ) +#define GET_DAC1() GET_REGISTER( "mfspr %0,1014" ) +#define SET_DAC1(val) SET_REGISTER( "mtspr 1014,%0", val ) +#define GET_DAC2() GET_REGISTER( "mfspr %0,1015" ) +#define SET_DAC2(val) SET_REGISTER( "mtspr 1015,%0", val ) +#define GET_DCCR() GET_REGISTER( "mfspr %0,1018" ) +#define SET_DCCR(val) SET_REGISTER( "mtspr 1018,%0", val ) +#define GET_ICCR() GET_REGISTER( "mfspr %0,1019" ) +#define SET_ICCR(val) SET_REGISTER( "mtspr 1019,%0", val ) + +#endif /* _REGS_H */ + + +/* + * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks + * All rights reserved. + * + * Redistribution and use in source and binary forms are freely + * permitted provided that the above copyright notice and this + * paragraph and the following disclaimer are duplicated in all + * such forms. + * + * This software is provided "AS IS" and without any express or + * implied warranties, including, without limitation, the implied + * warranties of merchantability and fitness for a particular + * purpose. + */ diff --git a/include/bedbug/tables.h b/include/bedbug/tables.h new file mode 100755 index 0000000..66cf8ea --- /dev/null +++ b/include/bedbug/tables.h @@ -0,0 +1,601 @@ +/* $Id$ */ + +#ifndef TABLES_H +#define TABLES_H + +/* This is only included by common/bedbug.c, and depends on the following + * files to already be included + * common.h + * bedbug/bedbug.h + * bedbug/ppc.h + * bedbug/regs.h + */ + +struct operand operands[] = { + /*Field Name Bits Shift Hint Position */ + /*----- ------ ----- ----- ---- ------------ */ + { O_AA, "O_AA", 1, 1, OH_SILENT }, /* 30 */ + { O_BD, "O_BD", 14, 2, OH_ADDR }, /* 16-29 */ + { O_BI, "O_BI", 5, 16, 0 }, /* 11-15 */ + { O_BO, "O_BO", 5, 21, 0 }, /* 6-10 */ + { O_crbD, "O_crbD", 5, 21, 0 }, /* 6-10 */ + { O_crbA, "O_crbA", 5, 16, 0 }, /* 11-15 */ + { O_crbB, "O_crbB", 5, 11, 0 }, /* 16-20 */ + { O_CRM, "O_CRM", 8, 12, 0 }, /* 12-19 */ + { O_d, "O_d", 15, 0, OH_OFFSET }, /* 16-31 */ + { O_frC, "O_frC", 5, 6, 0 }, /* 21-25 */ + { O_frD, "O_frD", 5, 21, 0 }, /* 6-10 */ + { O_frS, "O_frS", 5, 21, 0 }, /* 6-10 */ + { O_IMM, "O_IMM", 4, 12, 0 }, /* 16-19 */ + { O_LI, "O_LI", 24, 2, OH_ADDR }, /* 6-29 */ + { O_LK, "O_LK", 1, 0, OH_SILENT }, /* 31 */ + { O_MB, "O_MB", 5, 6, 0 }, /* 21-25 */ + { O_ME, "O_ME", 5, 1, 0 }, /* 26-30 */ + { O_NB, "O_NB", 5, 11, 0 }, /* 16-20 */ + { O_OE, "O_OE", 1, 10, OH_SILENT }, /* 21 */ + { O_rA, "O_rA", 5, 16, OH_REG }, /* 11-15 */ + { O_rB, "O_rB", 5, 11, OH_REG }, /* 16-20 */ + { O_Rc, "O_Rc", 1, 0, OH_SILENT }, /* 31 */ + { O_rD, "O_rD", 5, 21, OH_REG }, /* 6-10 */ + { O_rS, "O_rS", 5, 21, OH_REG }, /* 6-10 */ + { O_SH, "O_SH", 5, 11, 0 }, /* 16-20 */ + { O_SIMM, "O_SIMM", 16, 0, 0 }, /* 16-31 */ + { O_SR, "O_SR", 4, 16, 0 }, /* 12-15 */ + { O_TO, "O_TO", 5, 21, 0 }, /* 6-10 */ + { O_UIMM, "O_UIMM", 16, 0, 0 }, /* 16-31 */ + { O_crfD, "O_crfD", 3, 23, 0 }, /* 6- 8 */ + { O_crfS, "O_crfS", 3, 18, 0 }, /* 11-13 */ + { O_L, "O_L", 1, 21, 0 }, /* 10 */ + { O_spr, "O_spr", 10, 11, OH_SPR }, /* 11-20 */ + { O_tbr, "O_tbr", 10, 11, OH_TBR }, /* 11-20 */ + { O_cr2, "O_cr2", 0, 0, OH_LITERAL }, /* "cr2" */ +}; + +const unsigned int n_operands = sizeof(operands) / sizeof(operands[0]); + +/* A note about the fields array in the opcodes structure: + The operands are listed in the order they appear in the output. + + This table is arranged in numeric order of the opcode. Note that some + opcodes have defined bits in odd places so not all forms of a command + will be in the same place. This is done so that a binary search can be + done to find the opcodes. Note that table D.2 in the MPC860 User's + Manual "Instructions Sorted by Opcode" does not account for these + bit locations */ + +struct opcode opcodes[] = { + { D_OPCODE(3), D_MASK, {O_TO, O_rA, O_SIMM, 0}, + 0, "twi", 0 }, + { D_OPCODE(7), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "mulli", 0 }, + { D_OPCODE(8), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "subfic", 0 }, + { D_OPCODE(10), D_MASK, {O_crfD, O_L, O_rA, O_UIMM, 0}, + 0, "cmpli", 0 }, + { D_OPCODE(11), D_MASK, {O_crfD, O_L, O_rA, O_SIMM, 0}, + 0, "cmpi", 0 }, + { D_OPCODE(12), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "addic", 0 }, + { D_OPCODE(13), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "addic.", 0 }, + { D_OPCODE(14), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "addi", H_RA0_IS_0 }, + { D_OPCODE(15), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "addis", H_RA0_IS_0|H_IMM_HIGH }, + { B_OPCODE(16,0,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, + handle_bc, "bc", H_RELATIVE }, + { B_OPCODE(16,0,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, + 0, "bcl", H_RELATIVE }, + { B_OPCODE(16,1,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, + 0, "bca", 0 }, + { B_OPCODE(16,1,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, + 0, "bcla", 0 }, + { SC_OPCODE(17), SC_MASK, {0}, + 0, "sc", 0 }, + { I_OPCODE(18,0,0), I_MASK, {O_LI, O_AA, O_LK, 0}, + 0, "b", H_RELATIVE }, + { I_OPCODE(18,0,1), I_MASK, {O_LI, O_AA, O_LK, 0}, + 0, "bl", H_RELATIVE }, + { I_OPCODE(18,1,0), I_MASK, {O_LI, O_AA, O_LK, 0}, + 0, "ba", 0 }, + { I_OPCODE(18,1,1), I_MASK, {O_LI, O_AA, O_LK, 0}, + 0, "bla", 0 }, + { XL_OPCODE(19,0,0), XL_MASK, {O_crfD, O_crfS}, + 0, "mcrf", 0 }, + { XL_OPCODE(19,16,0), XL_MASK, {O_BO, O_BI, O_LK, 0}, + 0, "bclr", 0 }, + { XL_OPCODE(19,16,1), XL_MASK, {O_BO, O_BI, O_LK, 0}, + 0, "bclrl", 0 }, + { XL_OPCODE(19,33,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "crnor", 0 }, + { XL_OPCODE(19,50,0), XL_MASK, {0}, + 0, "rfi", 0 }, + { XL_OPCODE(19,129,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "crandc", 0 }, + { XL_OPCODE(19,150,0), XL_MASK, {0}, + 0, "isync", 0 }, + { XL_OPCODE(19,193,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "crxor", 0 }, + { XL_OPCODE(19,225,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "crnand", 0 }, + { XL_OPCODE(19,257,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "crand", 0 }, + { XL_OPCODE(19,289,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "creqv", 0 }, + { XL_OPCODE(19,417,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "crorc", 0 }, + { XL_OPCODE(19,449,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "cror", 0 }, + { XL_OPCODE(19,528,0), XL_MASK, {O_BO, O_BI, O_LK, 0}, + 0, "bcctr", 0 }, + { XL_OPCODE(19,528,1), XL_MASK, {O_BO, O_BI, O_LK, 0}, + 0, "bcctrl", 0 }, + { M_OPCODE(20,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, + 0, "rlwimi", 0 }, + { M_OPCODE(20,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, + 0, "rlwimi.", 0 }, + { M_OPCODE(21,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, + 0, "rlwinm", 0 }, + { M_OPCODE(21,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, + 0, "rlwinm.", 0 }, + { M_OPCODE(23,0), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0}, + 0, "rlwnm", 0 }, + { M_OPCODE(23,1), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0}, + 0, "rlwnm.", 0 }, + { D_OPCODE(24), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "ori", 0 }, + { D_OPCODE(25), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "oris", H_IMM_HIGH }, + { D_OPCODE(26), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "xori", 0 }, + { D_OPCODE(27), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "xoris", H_IMM_HIGH }, + { D_OPCODE(28), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "andi.", 0 }, + { D_OPCODE(29), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "andis.", H_IMM_HIGH }, + { X_OPCODE(31,0,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0}, + 0, "cmp", 0 }, + { X_OPCODE(31,4,0), X_MASK, {O_TO, O_rA, O_rB, 0}, + 0, "tw", 0 }, + { XO_OPCODE(31,8,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfc", 0 }, + { XO_OPCODE(31,8,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfc.", 0 }, + { XO_OPCODE(31,10,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addc", 0 }, + { XO_OPCODE(31,10,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addc.", 0 }, + { XO_OPCODE(31,11,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, + 0, "mulhwu", 0 }, + { XO_OPCODE(31,11,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, + 0, "mulhwu.", 0 }, + { X_OPCODE(31,19,0), X_MASK, {O_rD, 0}, + 0, "mfcr", 0 }, + { X_OPCODE(31,20,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lwarx", H_RA0_IS_0 }, + { X_OPCODE(31,23,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lwzx", H_RA0_IS_0 }, + { X_OPCODE(31,24,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "slw", 0 }, + { X_OPCODE(31,24,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "slw.", 0 }, + { X_OPCODE(31,26,0), X_MASK, {O_rA, O_rS, O_Rc, 0 }, + 0, "cntlzw", 0 }, + { X_OPCODE(31,26,1), X_MASK, {O_rA, O_rS, O_Rc, 0}, + 0, "cntlzw.", 0 }, + { X_OPCODE(31,28,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "and", 0 }, + { X_OPCODE(31,28,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "and.", 0 }, + { X_OPCODE(31,32,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0}, + 0, "cmpl", 0 }, + { XO_OPCODE(31,40,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subf", 0 }, + { XO_OPCODE(31,40,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subf.", 0 }, + { X_OPCODE(31,54,0), X_MASK, {O_rA, O_rB, 0}, + 0, "dcbst", H_RA0_IS_0 }, + { X_OPCODE(31,55,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lwzux", 0 }, + { X_OPCODE(31,60,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "andc", 0 }, + { X_OPCODE(31,60,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "andc.", 0 }, + { XO_OPCODE(31,75,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, + 0, "mulhw", 0 }, + { XO_OPCODE(31,75,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, + 0, "mulhw.", 0 }, + { X_OPCODE(31,83,0), X_MASK, {O_rD, 0}, + 0, "mfmsr", 0 }, + { X_OPCODE(31,86,0), X_MASK, {O_rA, O_rB, 0}, + 0, "dcbf", H_RA0_IS_0 }, + { X_OPCODE(31,87,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lbzx", H_RA0_IS_0 }, + { XO_OPCODE(31,104,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "neg", 0 }, + { XO_OPCODE(31,104,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "neg.", 0 }, + { X_OPCODE(31,119,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lbzux", 0 }, + { X_OPCODE(31,124,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "nor", 0 }, + { X_OPCODE(31,124,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "nor.", 0 }, + { XO_OPCODE(31,136,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfe", 0 }, + { XO_OPCODE(31,136,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfe.", 0 }, + { XO_OPCODE(31,138,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "adde", 0 }, + { XO_OPCODE(31,138,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "adde.", 0 }, + { XFX_OPCODE(31,144,0), XFX_MASK, {O_CRM, O_rS, 0}, + 0, "mtcrf", 0 }, + { X_OPCODE(31,146,0), X_MASK, {O_rS, 0}, + 0, "mtmsr", 0 }, + { X_OPCODE(31,150,1), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "stwcx.", 0 }, + { X_OPCODE(31,151,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "stwx", 0 }, + { X_OPCODE(31,183,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "stwux", 0 }, + { XO_OPCODE(31,200,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfze", 0 }, + { XO_OPCODE(31,200,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfze.", 0 }, + { XO_OPCODE(31,202,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addze", 0 }, + { XO_OPCODE(31,202,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addze.", 0 }, + { X_OPCODE(31,210,0), X_MASK, {O_SR, O_rS, 0}, + 0, "mtsr", 0 }, + { X_OPCODE(31,215,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "stbx", H_RA0_IS_0 }, + { XO_OPCODE(31,232,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfme", 0 }, + { XO_OPCODE(31,232,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfme.", 0 }, + { XO_OPCODE(31,234,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addme", 0 }, + { XO_OPCODE(31,234,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addme.", 0 }, + { XO_OPCODE(31,235,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "mullw", 0 }, + { XO_OPCODE(31,235,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "mullw.", 0 }, + { X_OPCODE(31,242,0), X_MASK, {O_rS, O_rB, 0}, + 0, "mtsrin", 0 }, + { X_OPCODE(31,246,0), X_MASK, {O_rA, O_rB, 0}, + 0, "dcbtst", H_RA0_IS_0 }, + { X_OPCODE(31,247,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "stbux", 0 }, + { XO_OPCODE(31,266,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "add", 0 }, + { XO_OPCODE(31,266,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "add.", 0 }, + { X_OPCODE(31,278,0), X_MASK, {O_rA, O_rB, 0}, + 0, "dcbt", H_RA0_IS_0 }, + { X_OPCODE(31,279,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lhzx", H_RA0_IS_0 }, + { X_OPCODE(31,284,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "eqv", 0 }, + { X_OPCODE(31,284,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "eqv.", 0 }, + { X_OPCODE(31,306,0), X_MASK, {O_rB, 0}, + 0, "tlbie", 0 }, + { X_OPCODE(31,310,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "eciwx", H_RA0_IS_0 }, + { X_OPCODE(31,311,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lhzux", 0 }, + { X_OPCODE(31,316,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "xor", 0 }, + { X_OPCODE(31,316,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "xor.", 0 }, + { XFX_OPCODE(31,339,0), XFX_MASK, {O_rD, O_spr, 0}, + 0, "mfspr", 0 }, + { X_OPCODE(31,343,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lhax", H_RA0_IS_0 }, + { X_OPCODE(31,370,0), X_MASK, {0}, + 0, "tlbia", 0 }, + { XFX_OPCODE(31,371,0), XFX_MASK, {O_rD, O_tbr, 0}, + 0, "mftb", 0 }, + { X_OPCODE(31,375,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lhaux", 0 }, + { X_OPCODE(31,407,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "sthx", H_RA0_IS_0 }, + { X_OPCODE(31,412,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "orc", 0 }, + { X_OPCODE(31,412,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "orc.", 0 }, + { X_OPCODE(31,438,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "ecowx", H_RA0_IS_0 }, + { X_OPCODE(31,439,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "sthux", 0 }, + { X_OPCODE(31,444,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "or", 0 }, + { X_OPCODE(31,444,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "or.", 0 }, + { XO_OPCODE(31,459,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divwu", 0 }, + { XO_OPCODE(31,459,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divwu.", 0 }, + { XFX_OPCODE(31,467,0), XFX_MASK, {O_spr, O_rS, 0}, + 0, "mtspr", 0 }, + { X_OPCODE(31,470,0), X_MASK, {O_rA, O_rB, 0}, + 0, "dcbi", H_RA0_IS_0 }, + { X_OPCODE(31,476,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "nand", 0 }, + { X_OPCODE(31,476,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc,0}, + 0, "nand.", 0 }, + { XO_OPCODE(31,491,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divw", 0 }, + { XO_OPCODE(31,491,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divw.", 0 }, + { X_OPCODE(31,512,0), X_MASK, {O_crfD, 0}, + 0, "mcrxr", 0 }, + { XO_OPCODE(31,8,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfco", 0 }, + { XO_OPCODE(31,8,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfco.", 0 }, + { XO_OPCODE(31,10,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addco", 0 }, + { XO_OPCODE(31,10,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addco.", 0 }, + { X_OPCODE(31,533,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lswx", H_RA0_IS_0 }, + { X_OPCODE(31,534,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lwbrx", H_RA0_IS_0 }, + { X_OPCODE(31,536,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "srw", 0 }, + { X_OPCODE(31,536,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "srw.", 0 }, + { XO_OPCODE(31,40,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfo", 0 }, + { XO_OPCODE(31,40,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfo.", 0 }, + { X_OPCODE(31,566,0), X_MASK, {0}, + 0, "tlbsync", 0 }, + { X_OPCODE(31,595,0), X_MASK, {O_rD, O_SR, 0}, + 0, "mfsr", 0 }, + { X_OPCODE(31,597,0), X_MASK, {O_rD, O_rA, O_NB, 0}, + 0, "lswi", H_RA0_IS_0 }, + { X_OPCODE(31,598,0), X_MASK, {0}, + 0, "sync", 0 }, + { XO_OPCODE(31,104,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "nego", 0 }, + { XO_OPCODE(31,104,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "nego.", 0 }, + { XO_OPCODE(31,136,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfeo", 0 }, + { XO_OPCODE(31,136,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfeo.", 0 }, + { XO_OPCODE(31,138,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addeo", 0 }, + { XO_OPCODE(31,138,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addeo.", 0 }, + { X_OPCODE(31,659,0), X_MASK, {O_rD, O_rB, 0}, + 0, "mfsrin", 0 }, + { X_OPCODE(31,661,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "stswx", H_RA0_IS_0 }, + { X_OPCODE(31,662,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "stwbrx", H_RA0_IS_0 }, + { XO_OPCODE(31,200,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfzeo", 0 }, + { XO_OPCODE(31,200,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfzeo.", 0 }, + { XO_OPCODE(31,202,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addzeo", 0 }, + { XO_OPCODE(31,202,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addzeo.", 0 }, + { X_OPCODE(31,725,0), X_MASK, {O_rS, O_rA, O_NB, 0}, + 0, "stswi", H_RA0_IS_0 }, + { XO_OPCODE(31,232,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfmeo", 0 }, + { XO_OPCODE(31,232,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfmeo.", 0 }, + { XO_OPCODE(31,234,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addmeo", 0 }, + { XO_OPCODE(31,234,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addmeo.", 0 }, + { XO_OPCODE(31,235,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "mullwo", 0 }, + { XO_OPCODE(31,235,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "mullwo.", 0 }, + { XO_OPCODE(31,266,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addo", 0 }, + { XO_OPCODE(31,266,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addo.", 0 }, + { X_OPCODE(31,790,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lhbrx", H_RA0_IS_0 }, + { X_OPCODE(31,792,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "sraw", 0 }, + { X_OPCODE(31,792,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "sraw.", 0 }, + { X_OPCODE(31,824,0), X_MASK, {O_rA, O_rS, O_SH, O_Rc, 0}, + 0, "srawi", 0 }, + { X_OPCODE(31,824,1), X_MASK, {O_rA, O_rS, O_SH, O_Rc, 0}, + 0, "srawi.", 0 }, + { X_OPCODE(31,854,0), X_MASK, {0}, + 0, "eieio", 0 }, + { X_OPCODE(31,918,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "sthbrx", H_RA0_IS_0 }, + { X_OPCODE(31,922,0), X_MASK, {O_rA, O_rS, O_Rc, 0}, + 0, "extsh", 0 }, + { X_OPCODE(31,922,1), X_MASK, {O_rA, O_rS, O_Rc, 0}, + 0, "extsh.", 0 }, + { X_OPCODE(31,954,0), X_MASK, {O_rA, O_rS, O_Rc, 0}, + 0, "extsb", 0 }, + { X_OPCODE(31,954,1), X_MASK, {O_rA, O_rS, O_Rc, 0}, + 0, "extsb.", 0 }, + { XO_OPCODE(31,459,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divwuo", 0 }, + { XO_OPCODE(31,459,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divwuo.", 0 }, + { X_OPCODE(31,978,0), X_MASK, {O_rB, 0}, + 0, "tlbld", 0 }, + { X_OPCODE(31,982,0), X_MASK, {O_rA, O_rB, 0}, + 0, "icbi", H_RA0_IS_0 }, + { XO_OPCODE(31,491,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divwo", 0 }, + { XO_OPCODE(31,491,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divwo.", 0 }, + { X_OPCODE(31,1010,0), X_MASK, {O_rB, 0}, + 0, "tlbli", 0 }, + { X_OPCODE(31,1014,0), X_MASK, {O_rA, O_rB, 0}, + 0, "dcbz", H_RA0_IS_0 }, + { D_OPCODE(32), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lwz", H_RA0_IS_0 }, + { D_OPCODE(33), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lwzu", 0 }, + { D_OPCODE(34), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lbz", H_RA0_IS_0 }, + { D_OPCODE(35), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lbzu", 0 }, + { D_OPCODE(36), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stw", H_RA0_IS_0 }, + { D_OPCODE(37), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stwu", 0 }, + { D_OPCODE(38), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stb", H_RA0_IS_0 }, + { D_OPCODE(39), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stbu", 0 }, + { D_OPCODE(40), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lhz", H_RA0_IS_0 }, + { D_OPCODE(41), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lhzu", 0 }, + { D_OPCODE(42), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lha", H_RA0_IS_0 }, + { D_OPCODE(43), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lhau", 0 }, + { D_OPCODE(44), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "sth", H_RA0_IS_0 }, + { D_OPCODE(45), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "sthu", 0 }, + { D_OPCODE(46), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lmw", H_RA0_IS_0 }, + { D_OPCODE(47), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stmw", H_RA0_IS_0 }, +}; + +const unsigned int n_opcodes = sizeof(opcodes) / sizeof(opcodes[0]); + +struct spr_info spr_map[] = { + { SPR_XER, "XER" }, + { SPR_LR, "LR" }, + { SPR_CTR, "CTR" }, + { SPR_DSISR, "DSISR" }, + { SPR_DAR, "DAR" }, + { SPR_DEC, "DEC" }, + { SPR_SRR0, "SRR0" }, + { SPR_SRR1, "SRR1" }, + { SPR_EIE, "EIE" }, + { SPR_EID, "EID" }, + { SPR_CMPA, "CMPA" }, + { SPR_CMPB, "CMPB" }, + { SPR_CMPC, "CMPC" }, + { SPR_CMPD, "CMPD" }, + { SPR_ICR, "ICR" }, + { SPR_DER, "DER" }, + { SPR_COUNTA, "COUNTA" }, + { SPR_COUNTB, "COUNTB" }, + { SPR_CMPE, "CMPE" }, + { SPR_CMPF, "CMPF" }, + { SPR_CMPG, "CMPG" }, + { SPR_CMPH, "CMPH" }, + { SPR_LCTRL1, "LCTRL1" }, + { SPR_LCTRL2, "LCTRL2" }, + { SPR_ICTRL, "ICTRL" }, + { SPR_BAR, "BAR" }, + { SPR_USPRG0, "USPRG0" }, + { SPR_SPRG4_RO, "SPRG4_RO" }, + { SPR_SPRG5_RO, "SPRG5_RO" }, + { SPR_SPRG6_RO, "SPRG6_RO" }, + { SPR_SPRG7_RO, "SPRG7_RO" }, + { SPR_SPRG0, "SPRG0" }, + { SPR_SPRG1, "SPRG1" }, + { SPR_SPRG2, "SPRG2" }, + { SPR_SPRG3, "SPRG3" }, + { SPR_SPRG4, "SPRG4" }, + { SPR_SPRG5, "SPRG5" }, + { SPR_SPRG6, "SPRG6" }, + { SPR_SPRG7, "SPRG7" }, + { SPR_EAR, "EAR" }, + { SPR_TBL, "TBL" }, + { SPR_TBU, "TBU" }, + { SPR_IC_CST, "IC_CST" }, + { SPR_IC_ADR, "IC_ADR" }, + { SPR_IC_DAT, "IC_DAT" }, + { SPR_DC_CST, "DC_CST" }, + { SPR_DC_ADR, "DC_ADR" }, + { SPR_DC_DAT, "DC_DAT" }, + { SPR_DPDR, "DPDR" }, + { SPR_IMMR, "IMMR" }, + { SPR_MI_CTR, "MI_CTR" }, + { SPR_MI_AP, "MI_AP" }, + { SPR_MI_EPN, "MI_EPN" }, + { SPR_MI_TWC, "MI_TWC" }, + { SPR_MI_RPN, "MI_RPN" }, + { SPR_MD_CTR, "MD_CTR" }, + { SPR_M_CASID, "M_CASID" }, + { SPR_MD_AP, "MD_AP" }, + { SPR_MD_EPN, "MD_EPN" }, + { SPR_M_TWB, "M_TWB" }, + { SPR_MD_TWC, "MD_TWC" }, + { SPR_MD_RPN, "MD_RPN" }, + { SPR_M_TW, "M_TW" }, + { SPR_MI_DBCAM, "MI_DBCAM" }, + { SPR_MI_DBRAM0, "MI_DBRAM0" }, + { SPR_MI_DBRAM1, "MI_DBRAM1" }, + { SPR_MD_DBCAM, "MD_DBCAM" }, + { SPR_MD_DBRAM0, "MD_DBRAM0" }, + { SPR_MD_DBRAM1, "MD_DBRAM1" }, + { SPR_ZPR, "ZPR" }, + { SPR_PID, "PID" }, + { SPR_CCR0, "CCR0" }, + { SPR_IAC3, "IAC3" }, + { SPR_IAC4, "IAC4" }, + { SPR_DVC1, "DVC1" }, + { SPR_DVC2, "DVC2" }, + { SPR_SGR, "SGR" }, + { SPR_DCWR, "DCWR" }, + { SPR_SLER, "SLER" }, + { SPR_SU0R, "SU0R" }, + { SPR_DBCR1, "DBCR1" }, + { SPR_ICDBDR, "ICDBDR" }, + { SPR_ESR, "ESR" }, + { SPR_DEAR, "DEAR" }, + { SPR_EVPR, "EVPR" }, + { SPR_TSR, "TSR" }, + { SPR_TCR, "TCR" }, + { SPR_PIT, "PIT" }, + { SPR_SRR2, "SRR2" }, + { SPR_SRR3, "SRR3" }, + { SPR_DBSR, "DBSR" }, + { SPR_DBCR0, "DBCR0" }, + { SPR_IAC1, "IAC1" }, + { SPR_IAC2, "IAC2" }, + { SPR_DAC1, "DAC1" }, + { SPR_DAC2, "DAC2" }, + { SPR_DCCR, "DCCR" }, + { SPR_ICCR, "ICCR" }, +}; + +const unsigned int n_sprs = sizeof(spr_map) / sizeof(spr_map[0]); + +#endif + +/* + * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks + * All rights reserved. + * + * Redistribution and use in source and binary forms are freely + * permitted provided that the above copyright notice and this + * paragraph and the following disclaimer are duplicated in all + * such forms. + * + * This software is provided "AS IS" and without any express or + * implied warranties, including, without limitation, the implied + * warranties of merchantability and fitness for a particular + * purpose. + */ diff --git a/include/bedbug/type.h b/include/bedbug/type.h new file mode 100755 index 0000000..38ee9de --- /dev/null +++ b/include/bedbug/type.h @@ -0,0 +1,26 @@ +#ifndef _TYPE_BEDBUG_H +#define _TYPE_BEDBUG_H + +/* Supporting routines */ +int bedbug_puts (const char *); +void bedbug_init (void); +void bedbug860_init (void); +void do_bedbug_breakpoint (struct pt_regs *); +void bedbug_main_loop (unsigned long, struct pt_regs *); + + +typedef struct { + int hw_debug_enabled; + int stopped; + int current_bp; + struct pt_regs *regs; + + void (*do_break) (cmd_tbl_t *, int, int, char *[]); + void (*break_isr) (struct pt_regs *); + int (*find_empty) (void); + int (*set) (int, unsigned long); + int (*clear) (int); +} CPU_DEBUG_CTX; + + +#endif /* _TYPE_BEDBUG_H */ |