init commit via android 4.4 uboot

1 files changed, 785 insertions, 0 deletions

diff --git a/board/wmt/include/wmt_gpio.h b/board/wmt/include/wmt_gpio.h
new file mode 100755
index 0000000..e2e150b
--- /dev/null
+++ b/board/wmt/include/wmt_gpio.h
@@ -0,0 +1,785 @@
+/*++
+linux/arch/arm/mach-wmt/include/mach/wmt_gpio.h
+
+Copyright (c) 2013  WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under the
+terms of the GNU General Public License as published by the Free Software Foundation,
+either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program.  If not, see <http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+
+/* Be sure that virtual mapping is defined right */
+
+#ifndef __WMT_GPIO_H
+/* To assert that only one occurrence is included */
+#define __WMT_GPIO_H
+
+/*-------------------- EXPORTED PRIVATE CONSTANTS -----------------------------*/
+
+/*-------------------- EXPORTED PRIVATE TYPES----------------------------------*/
+
+/*-------------------- EXPORTED PRIVATE VARIABLES -----------------------------*/
+#ifdef XXX_C /* allocate memory for variables only in xxx.c */
+#       define EXTERN
+#else
+#       define EXTERN   extern
+#endif /* ifdef XXX_C */
+
+
+#undef EXTERN
+
+/*--------------------- EXPORTED PRIVATE MACROS -------------------------------*/
+#define __GPIO_BASE      0xD8110000
+
+#define GIRQ_LOW                        0x00            /* Input zero generate GPIO_IRQ signal */
+#define GIRQ_HIGH                       0x01            /* Input one generate GPIO_IRQ signal */
+#define GIRQ_FALLING            0x02            /* Falling edge generate GPIO_IRQ signal */
+#define GIRQ_RISING                     0x03            /* Rising edge generate GPIO_IRQ signal */
+#define GIRQ_BOTHEDGE           0x04
+#define GIRQ_TYPEMASK           0x07
+#define GIRQ_TYPE(idx, type)    ((type & GIRQ_TYPEMASK) << (idx * 8)) /* idx must be 0-3 */
+#define GIRQ_EN_STS(idx)                ( 1 << ((idx+1)*8-1) )  /* idx must be 0-3 */
+
+#define GPIO_ID_GP0_BYTE_ADDR					(__GPIO_BASE + 0x00  )/* [0x0] */
+#define GPIO_ID_GP1_BYTE_ADDR 					(__GPIO_BASE + 0x01  )/* [0x1] */
+#define GPIO_ID_GP2_BYTE_ADDR					(__GPIO_BASE + 0x02  )/* [0x2] */
+#define GPIO_ID_GP4_VDOUT_7_0_BYTE_ADDR			(__GPIO_BASE + 0x04  )/* [0x4] */
+#define GPIO_ID_GP5_VDOUT_15_8_BYTE_ADDR		(__GPIO_BASE + 0x05  )/* [0x5] */
+#define GPIO_ID_GP6_VDOUT_23_16_BYTE_ADDR		(__GPIO_BASE + 0x06  )/* [0x6] */
+#define GPIO_ID_GP7_VD_BYTE_ADDR				(__GPIO_BASE + 0x07  )/* [0x7] */
+#define GPIO_ID_GP8_VDIN_BYTE_ADDR				(__GPIO_BASE + 0x08  )/* [0x8] */
+#define GPIO_ID_GP9_VSYNC_BYTE_ADDR 			(__GPIO_BASE + 0x09  )/* [0x9] */
+#define GPIO_ID_GP10_I2S_BYTE_ADDR				(__GPIO_BASE + 0x0A  )/* [0xA] */
+#define GPIO_ID_GP11_I2S_BYTE_ADDR      		(__GPIO_BASE + 0x0B  )/* [0xB] */
+#define GPIO_ID_GP12_SPI_BYTE_ADDR				(__GPIO_BASE + 0x0C  )/* [0xC] */
+#define GPIO_ID_GP13_SD0_BYTE_ADDR   			(__GPIO_BASE + 0x0D  )/* [0xD] */
+#define GPIO_ID_GP14_NAND_SD1_BYTE_ADDR			(__GPIO_BASE + 0x0E  )/* [0xE] */
+#define GPIO_ID_GP15_NAND_BYTE_ADDR				(__GPIO_BASE + 0x0F  )/* [0xF] */
+#define GPIO_ID_GP16_NAND_SD1_BYTE_ADDR			(__GPIO_BASE + 0x10  )/* [0x10] */
+#define GPIO_ID_GP17_I2C_BYTE_ADDR       		(__GPIO_BASE + 0x11  )/* [0x11] */
+#define GPIO_ID_GP18_UART_BYTE_ADDR				(__GPIO_BASE + 0x12  )/* [0x12] */
+#define GPIO_ID_GP19_SD2_BYTE_ADDR   	    	(__GPIO_BASE + 0x13  )/* [0x13] */
+#define GPIO_ID_GP20_PWM0_BYTE_ADDR       		(__GPIO_BASE + 0x14  )/* [0x14] */
+#define GPIO_ID_GP21_HDMI_BYTE_ADDR       		(__GPIO_BASE + 0x15  )/* [0x15] */
+#define GPIO_ID_GP23_I2C3_BYTE_ADDR	    	   	(__GPIO_BASE + 0x17  )/* [0x17] */
+#define GPIO_ID_GP24_SF_BYTE_ADDR				(__GPIO_BASE + 0x18  )/* [0x18] */
+#define GPIO_ID_GP26_PCM_BYTE_ADDR       		(__GPIO_BASE + 0x1A  )/* [0x1A] */
+#define GPIO_ID_GP60_USB_BYTE_ADDR				(__GPIO_BASE + 0x3C  )/* [0x3C] */
+#define GPIO_ID_GP62_WAKEUP_SUS_BYTE_ADDR		(__GPIO_BASE + 0x3E  )/* [0x3E] */
+#define GPIO_ID_GP63_SD02CD_BYTE_ADDR			(__GPIO_BASE + 0x3F  )/* [0x3F] */
+#define GPIO_CTRL_GP0_BYTE_ADDR 				(__GPIO_BASE + 0x40  )/* [0x40] */
+#define GPIO_CTRL_GP1_BYTE_ADDR 				(__GPIO_BASE + 0x41  )/* [0x41] */
+#define GPIO_CTRL_GP2_BYTE_ADDR 				(__GPIO_BASE + 0x42  )/* [0x42] */
+#define GPIO_CTRL_GP4_VDOUT_7_0_BYTE_ADDR		(__GPIO_BASE + 0x44  )/* [0x44] */
+#define GPIO_CTRL_GP5_VDOUT_15_8_BYTE_ADDR		(__GPIO_BASE + 0x45  )/* [0x45] */
+#define GPIO_CTRL_GP6_VDOUT_23_16_BYTE_ADDR		(__GPIO_BASE + 0x46  )/* [0x46] */
+#define GPIO_CTRL_GP7_VD_BYTE_ADDR				(__GPIO_BASE + 0x47  )/* [0x47] */
+#define GPIO_CTRL_GP8_VDIN_BYTE_ADDR			(__GPIO_BASE + 0x48  )/* [0x48] */
+#define GPIO_CTRL_GP9_VSYNC_BYTE_ADDR 			(__GPIO_BASE + 0x49  )/* [0x49] */
+#define GPIO_CTRL_GP10_I2S_BYTE_ADDR			(__GPIO_BASE + 0x4A  )/* [0x4A] */
+#define GPIO_CTRL_GP11_I2S_BYTE_ADDR      		(__GPIO_BASE + 0x4B  )/* [0x4B] */
+#define GPIO_CTRL_GP12_SPI_BYTE_ADDR			(__GPIO_BASE + 0x4C  )/* [0x4C] */
+#define GPIO_CTRL_GP13_SD0_BYTE_ADDR       		(__GPIO_BASE + 0x4D  )/* [0x4D] */
+#define GPIO_CTRL_GP14_NAND_SD1_BYTE_ADDR		(__GPIO_BASE + 0x4E  )/* [0x4E] */
+#define GPIO_CTRL_GP15_NAND_BYTE_ADDR			(__GPIO_BASE + 0x4F  )/* [0x4F] */
+#define GPIO_CTRL_GP16_NAND_SD1_BYTE_ADDR		(__GPIO_BASE + 0x50  )/* [0x50] */
+#define GPIO_CTRL_GP17_I2C_BYTE_ADDR       		(__GPIO_BASE + 0x51  )/* [0x51] */
+#define GPIO_CTRL_GP18_UART_BYTE_ADDR			(__GPIO_BASE + 0x52  )/* [0x52] */
+#define GPIO_CTRL_GP19_SD2_BYTE_ADDR   	    	(__GPIO_BASE + 0x53  )/* [0x53] */
+#define GPIO_CTRL_GP20_PWM0_BYTE_ADDR       	(__GPIO_BASE + 0x54  )/* [0x54] */
+#define GPIO_CTRL_GP21_HDMI_BYTE_ADDR       	(__GPIO_BASE + 0x55  )/* [0x55] */
+#define GPIO_CTRL_GP23_I2C3_BYTE_ADDR	    	(__GPIO_BASE + 0x57  )/* [0x57] */
+#define GPIO_CTRL_GP24_SF_BYTE_ADDR				(__GPIO_BASE + 0x58  )/* [0x58] */
+#define GPIO_CTRL_GP26_PCM_BYTE_ADDR       		(__GPIO_BASE + 0x5A  )/* [0x5A] */
+#define GPIO_CTRL_GP60_USB_BYTE_ADDR			(__GPIO_BASE + 0x7C  )/* [0x7C] */
+#define GPIO_CTRL_GP62_WAKEUP_SUS_BYTE_ADDR		(__GPIO_BASE + 0x7E  )/* [0x7E] */
+#define GPIO_CTRL_GP63_SD02CD_BYTE_ADDR			(__GPIO_BASE + 0x7F  )/* [0x7F] */
+#define GPIO_OC_GP0_BYTE_ADDR 					(__GPIO_BASE + 0x80  )/* [0x80] */
+#define GPIO_OC_GP1_BYTE_ADDR 					(__GPIO_BASE + 0x81  )/* [0x81] */
+#define GPIO_OC_GP2_BYTE_ADDR					(__GPIO_BASE + 0x82  )/* [0x82] */
+#define GPIO_OC_GP4_VDOUT_7_0_BYTE_ADDR			(__GPIO_BASE + 0x84  )/* [0x84] */
+#define GPIO_OC_GP5_VDOUT_15_8_BYTE_ADDR		(__GPIO_BASE + 0x85  )/* [0x85] */
+#define GPIO_OC_GP6_VDOUT_23_16_BYTE_ADDR		(__GPIO_BASE + 0x86  )/* [0x86] */
+#define GPIO_OC_GP7_VD_BYTE_ADDR				(__GPIO_BASE + 0x87  )/* [0x87] */
+#define GPIO_OC_GP8_VDIN_BYTE_ADDR				(__GPIO_BASE + 0x88  )/* [0x88] */
+#define GPIO_OC_GP9_VSYNC_BYTE_ADDR 			(__GPIO_BASE + 0x89  )/* [0x89] */
+#define GPIO_OC_GP10_I2S_BYTE_ADDR				(__GPIO_BASE + 0x8A  )/* [0x8A] */
+#define GPIO_OC_GP11_I2S_BYTE_ADDR      		(__GPIO_BASE + 0x8B  )/* [0x8B] */
+#define GPIO_OC_GP12_SPI_BYTE_ADDR				(__GPIO_BASE + 0x8C  )/* [0x8C] */
+#define GPIO_OC_GP13_SD0_BYTE_ADDR   			(__GPIO_BASE + 0x8D  )/* [0x8D] */
+#define GPIO_OC_GP14_NAND_SD1_BYTE_ADDR			(__GPIO_BASE + 0x8E  )/* [0x8E] */
+#define GPIO_OC_GP15_NAND_BYTE_ADDR				(__GPIO_BASE + 0x8F  )/* [0x8F] */
+#define GPIO_OC_GP16_NAND_SD1_BYTE_ADDR			(__GPIO_BASE + 0x90  )/* [0x90] */
+#define GPIO_OC_GP17_I2C_BYTE_ADDR       		(__GPIO_BASE + 0x91  )/* [0x91] */
+#define GPIO_OC_GP18_UART_BYTE_ADDR				(__GPIO_BASE + 0x92  )/* [0x92] */
+#define GPIO_OC_GP19_SD2_BYTE_ADDR   	    	(__GPIO_BASE + 0x93  )/* [0x93] */
+#define GPIO_OC_GP20_PWM0_BYTE_ADDR       		(__GPIO_BASE + 0x94  )/* [0x94] */
+#define GPIO_OC_GP21_HDMI_BYTE_ADDR       		(__GPIO_BASE + 0x95  )/* [0x95] */
+#define GPIO_OC_GP22_I2C3_BYTE_ADDR	     	  	(__GPIO_BASE + 0x96  )/* [0x96] */
+#define GPIO_OC_GP24_SF_BYTE_ADDR				(__GPIO_BASE + 0x98  )/* [0x98] */
+#define GPIO_OC_GP26_PCM_BYTE_ADDR       		(__GPIO_BASE + 0x9A  )/* [0x9A] */
+#define GPIO_OC_GP60_USB_BYTE_ADDR				(__GPIO_BASE + 0xBC  )/* [0xBC] */
+#define GPIO_OC_GP62_WAKEUP_SUS_BYTE_ADDR		(__GPIO_BASE + 0xBE  )/* [0xBE] */
+#define GPIO_OC_GP63_SD02CD_BYTE_ADDR			(__GPIO_BASE + 0xBF  )/* [0xBF] */
+#define GPIO_OD_GP0_BYTE_ADDR 					(__GPIO_BASE + 0xC0  )/* [0xC0] */
+#define GPIO_OD_GP1_BYTE_ADDR 					(__GPIO_BASE + 0xC1  )/* [0xC1] */
+#define GPIO_OD_GP2_BYTE_ADDR					(__GPIO_BASE + 0xC2  )/* [0xC2] */
+#define GPIO_OD_GP4_VDOUT_7_0_BYTE_ADDR			(__GPIO_BASE + 0xC4  )/* [0xC4] */
+#define GPIO_OD_GP5_VDOUT_15_8_BYTE_ADDR		(__GPIO_BASE + 0xC5  )/* [0xC5] */
+#define GPIO_OD_GP6_VDOUT_23_16_BYTE_ADDR		(__GPIO_BASE + 0xC6  )/* [0xC6] */
+#define GPIO_OD_GP7_VD_BYTE_ADDR				(__GPIO_BASE + 0xC7  )/* [0xC7] */
+#define GPIO_OD_GP8_VDIN_BYTE_ADDR				(__GPIO_BASE + 0xC8  )/* [0xC8] */
+#define GPIO_OD_GP9_VSYNC_BYTE_ADDR 			(__GPIO_BASE + 0xC9  )/* [0xC9] */
+#define GPIO_OD_GP10_I2S_BYTE_ADDR				(__GPIO_BASE + 0xCA  )/* [0xCA] */
+#define GPIO_OD_GP11_I2S_BYTE_ADDR      		(__GPIO_BASE + 0xCB  )/* [0xCB] */
+#define GPIO_OD_GP12_SPI_BYTE_ADDR				(__GPIO_BASE + 0xCC  )/* [0xCC] */
+#define GPIO_OD_GP13_SD0_BYTE_ADDR   			(__GPIO_BASE + 0xCD  )/* [0xCD] */
+#define GPIO_OD_GP14_NAND_SD1_BYTE_ADDR			(__GPIO_BASE + 0xCE  )/* [0xCE] */
+#define GPIO_OD_GP15_NAND_BYTE_ADDR				(__GPIO_BASE + 0xCF  )/* [0xCF] */
+#define GPIO_OD_GP16_NAND_SD1_BYTE_ADDR			(__GPIO_BASE + 0xD0  )/* [0xD0] */
+#define GPIO_OD_GP17_I2C_BYTE_ADDR       		(__GPIO_BASE + 0xD1  )/* [0xD1] */
+#define GPIO_OD_GP18_UART_BYTE_ADDR				(__GPIO_BASE + 0xD2  )/* [0xD2] */
+#define GPIO_OD_GP19_SD2_BYTE_ADDR   	    	(__GPIO_BASE + 0xD3  )/* [0xD3] */
+#define GPIO_OD_GP20_PWM0_BYTE_ADDR       		(__GPIO_BASE + 0xD4  )/* [0xD4] */
+#define GPIO_OD_GP21_HDMI_BYTE_ADDR       		(__GPIO_BASE + 0xD5  )/* [0xD5] */
+#define GPIO_OD_GP23_I2C3_BYTE_ADDR	       		(__GPIO_BASE + 0xD7  )/* [0xD7] */
+#define GPIO_OD_GP24_SF_BYTE_ADDR				(__GPIO_BASE + 0xD8  )/* [0xD8] */
+#define GPIO_OD_GP26_PCM_BYTE_ADDR       		(__GPIO_BASE + 0xDA  )/* [0xDA] */
+#define GPIO_OD_GP60_USB_BYTE_ADDR				(__GPIO_BASE + 0xFC  )/* [0xFC] */
+#define GPIO_OD_GP62_WAKEUP_SUS_BYTE_ADDR		(__GPIO_BASE + 0xFE  )/* [0xFE] */
+#define GPIO_OD_GP63_SD02CD_BYTE_ADDR			(__GPIO_BASE + 0xFF  )/* [0xFF] */
+#define STRAP_STATUS_ADDR					(__GPIO_BASE + 0x100  )/* [0x100 ~ 0x103] */
+#define AHB_CTRL_4BYTE_ADDR 				(__GPIO_BASE + 0x108  )/* [0x108 ~ 0x10B] */
+#define USB_OP_CTRL_4BYTE_ADDR				(__GPIO_BASE + 0x10C  )/* [0x10C ~ 0x10F] */
+#define BONDING_OPTION_4BYTE_ADDR			(__GPIO_BASE + 0x110  )/* [0x110 ~ 0x113] */
+#define PIN_SHARING_SEL_4BYTE_ADDR 			(__GPIO_BASE + 0x200  )/* [0x200 ~ 0x203] */
+#define TPIU_CLK_DATA_4BYTE_ADDR 			(__GPIO_BASE + 0x244  )/* [0x244 ~ 0x247] */
+#define GPIO0_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x300  )/* [0x300] */
+#define GPIO1_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x301  )/* [0x301] */
+#define GPIO2_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x302  )/* [0x302] */
+#define GPIO3_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x303  )/* [0x303] */
+#define GPIO4_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x304  )/* [0x304] */
+#define GPIO5_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x305  )/* [0x305] */
+#define GPIO6_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x306  )/* [0x306] */
+#define GPIO7_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x307  )/* [0x307] */
+#define GPIO8_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x308  )/* [0x308] */
+#define GPIO9_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x309  )/* [0x309] */
+#define GPIO10_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x30A  )/* [0x30A] */
+#define GPIO11_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x30B  )/* [0x30B] */
+#define GPIO12_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x30C  )/* [0x30C] */
+#define GPIO13_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x30D  )/* [0x30D] */
+#define GPIO18_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x30E  )/* [0x30E] */
+#define GPIO19_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x30F  )/* [0x30F] */
+#define VOUT20_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x310  )/* [0x310] */
+#define VOUT21_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x311  )/* [0x311] */
+#define VOUT22_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x312  )/* [0x312] */
+#define VOUT23_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x313  )/* [0x313] */
+#define GPIO20_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x314  )/* [0x314] */
+#define GPIO21_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x315  )/* [0x315] */
+#define GPIO22_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x316  )/* [0x316] */
+#define GPIO23_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x317  )/* [0x317] */
+#define GPIO24_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x318  )/* [0x318] */
+#define GPIO25_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x319  )/* [0x319] */
+#define GPIO0_INT_REQ_STS_ADDR				(__GPIO_BASE + 0x360  )/* [0x360] */
+#define GPIO1_INT_REQ_STS_ADDR				(__GPIO_BASE + 0x361  )/* [0x361] */
+#define GPIO2_INT_REQ_STS_ADDR				(__GPIO_BASE + 0x362  )/* [0x362] */
+#define GPIO3_INT_REQ_STS_ADDR				(__GPIO_BASE + 0x363  )/* [0x363] */
+#define DRV_DVO_CLK_BYTE_ADDR				(__GPIO_BASE + 0x402  )/* [0x402] */
+#define DRV_DVO_VDEN_BYTE_ADDR				(__GPIO_BASE + 0x403  )/* [0x403] */
+#define SD0_DPCTL_4BYTE_ADDR				(__GPIO_BASE + 0x404  )/* [0x404 ~ 0x407] */
+#define SD0_DNCTL_4BYTE_ADDR				(__GPIO_BASE + 0x408  )/* [0x408 ~ 0x40B] */
+#define DRV_SD0_USB_BYTE_ADDR				(__GPIO_BASE + 0x464  )/* [0x464] */	
+#define DRV_USB_SWOC0_BYTE_ADDR				(__GPIO_BASE + 0x465  )/* [0x465] */	
+#define DRV_USB_OC12_BYTE_ADDR				(__GPIO_BASE + 0x466  )/* [0x466] */
+#define DRV_USBOC3_CIR_BYTE_ADDR			(__GPIO_BASE + 0x467  )/* [0x467] */
+#define DRV_PWREN_BYTE_ADDR					(__GPIO_BASE + 0x468  )/* [0x468] */
+#define DRV_PWREN_WAKEUP0_BYTE_ADDR			(__GPIO_BASE + 0x469  )/* [0x469] */
+#define DRV_SUSGP01_BYTE_ADDR				(__GPIO_BASE + 0x46A  )/* [0x46A] */
+#define DRV_WAKEUP23_BYTE_ADDR				(__GPIO_BASE + 0x46B  )/* [0x46B] */
+#define DRV_WAKEUP45_BYTE_ADDR				(__GPIO_BASE + 0x46C  )/* [0x46C] */
+#define DRV_I2C_BYTE_ADDR					(__GPIO_BASE + 0x46D  )/* [0x46D] */
+#define DRV_HDMI_BYTE_ADDR					(__GPIO_BASE + 0x46E  )/* [0x46E] */	
+#define PULL_EN_GP0_BYTE_ADDR				(__GPIO_BASE + 0x480  )/* [0x480] */
+#define PULL_EN_GP1_BYTE_ADDR				(__GPIO_BASE + 0x481  )/* [0x481] */
+#define PULL_EN_GP2_BYTE_ADDR				(__GPIO_BASE + 0x482  )/* [0x482] */
+#define PULL_EN_GP4_VDOUT_7_0_BYTE_ADDR		(__GPIO_BASE + 0x484  )/* [0x484] */
+#define PULL_EN_GP5_VDOUT_15_8_BYTE_ADDR	(__GPIO_BASE + 0x485  )/* [0x485] */
+#define PULL_EN_GP6_VDOUT_23_16_BYTE_ADDR	(__GPIO_BASE + 0x486  )/* [0x486] */
+#define PULL_EN_GP7_VD_BYTE_ADDR     		(__GPIO_BASE + 0x487  )/* [0x487] */
+#define PULL_EN_GP8_VDIN_BYTE_ADDR   		(__GPIO_BASE + 0x488  )/* [0x488] */
+#define PULL_EN_GP9_VSYNC_BYTE_ADDR 		(__GPIO_BASE + 0x489  )/* [0x489] */
+#define PULL_EN_GP10_I2S_BYTE_ADDR 			(__GPIO_BASE + 0x48A  )/* [0x48A] */
+#define PULL_EN_GP11_I2S_BYTE_ADDR     		(__GPIO_BASE + 0x48B  )/* [0x48B] */
+#define PULL_EN_GP12_SPI_BYTE_ADDR			(__GPIO_BASE + 0x48C  )/* [0x48C] */
+#define PULL_EN_GP13_SD0_BYTE_ADDR       	(__GPIO_BASE + 0x48D  )/* [0x48D] */
+#define PULL_EN_GP14_NAND_BYTE_ADDR      	(__GPIO_BASE + 0x48E  )/* [0x48E] */
+#define PULL_EN_GP15_NAND_BYTE_ADDR			(__GPIO_BASE + 0x48F  )/* [0x48F] */
+#define PULL_EN_GP16_NANDIO_BYTE_ADDR		(__GPIO_BASE + 0x490  )/* [0x490] */
+#define PULL_EN_GP17_I2C_BYTE_ADDR			(__GPIO_BASE + 0x491  )/* [0x491] */
+#define PULL_EN_GP18_UART_BYTE_ADDR			(__GPIO_BASE + 0x492  )/* [0x492] */
+#define PULL_EN_GP19_SD2_BYTE_ADDR			(__GPIO_BASE + 0x493  )/* [0x493] */
+#define PULL_EN_GP20_PWM0_BYTE_ADDR			(__GPIO_BASE + 0x494  )/* [0x494] */
+#define PULL_EN_GP21_HDMI_BYTE_ADDR      	(__GPIO_BASE + 0x495  )/* [0x495] */
+#define PULL_EN_GP23_I2C3_BYTE_ADDR			(__GPIO_BASE + 0x497  )/* [0x497] */
+#define PULL_EN_GP24_SF_BYTE_ADDR			(__GPIO_BASE + 0x498  )/* [0x498] */
+#define PULL_EN_GP26_PCM_BYTE_ADDR			(__GPIO_BASE + 0x49A  )/* [0x49A] */
+#define PULL_EN_GP60_USB_BYTE_ADDR			(__GPIO_BASE + 0x4BC  )/* [0x4BC] */
+#define PULL_EN_GP62_WAKEUP_SUS_BYTE_ADDR	(__GPIO_BASE + 0x4BE  )/* [0x4BE] */
+#define PULL_EN_GP63_SD02_BYTE_ADDR			(__GPIO_BASE + 0x4BF  )/* [0x4BF] */
+#define PULL_CTRL_GP0_BYTE_ADDR				(__GPIO_BASE + 0x4C0  )/* [0x4C0] */
+#define PULL_CTRL_GP1_BYTE_ADDR				(__GPIO_BASE + 0x4C1  )/* [0x4C1] */
+#define PULL_CTRL_GP2_BYTE_ADDR				(__GPIO_BASE + 0x4C2  )/* [0x4C2] */
+#define PULL_CTRL_GP4_VDOUT_7_0_BYTE_ADDR	(__GPIO_BASE + 0x4C4  )/* [0x4C4] */
+#define PULL_CTRL_GP5_VDOUT_15_8_BYTE_ADDR	(__GPIO_BASE + 0x4C5  )/* [0x4C5] */
+#define PULL_CTRL_GP6_VDOUT_23_16_BYTE_ADDR	(__GPIO_BASE + 0x4C6  )/* [0x4C6] */
+#define PULL_CTRL_GP7_VD_BYTE_ADDR			(__GPIO_BASE + 0x4C7  )/* [0x4C7] */
+#define PULL_CTRL_GP8_VDIN_BYTE_ADDR		(__GPIO_BASE + 0x4C8  )/* [0x4C8] */
+#define PULL_CTRL_GP9_VSYNC_BYTE_ADDR		(__GPIO_BASE + 0x4C9  )/* [0x4C9] */
+#define PULL_CTRL_GP10_I2S_BYTE_ADDR		(__GPIO_BASE + 0x4CA  )/* [0x4CA] */
+#define PULL_CTRL_GP11_I2S_BYTE_ADDR		(__GPIO_BASE + 0x4CB  )/* [0x4CB] */
+#define PULL_CTRL_GP12_SPI_BYTE_ADDR		(__GPIO_BASE + 0x4CC  )/* [0x4CC] */
+#define PULL_CTRL_GP13_SD0_BYTE_ADDR		(__GPIO_BASE + 0x4CD  )/* [0x4CD] */
+#define PULL_CTRL_GP14_NAND_BYTE_ADDR       (__GPIO_BASE + 0x4CE  )/* [0x4CE] */
+#define PULL_CTRL_GP15_NAND_BYTE_ADDR		(__GPIO_BASE + 0x4CF  )/* [0x4CF] */
+#define PULL_CTRL_GP16_NANDIO_BYTE_ADDR		(__GPIO_BASE + 0x4D0  )/* [0x4D0] */
+#define PULL_CTRL_GP17_I2C_BYTE_ADDR     	(__GPIO_BASE + 0x4D1  )/* [0x4D1] */
+#define PULL_CTRL_GP18_UART_BYTE_ADDR     	(__GPIO_BASE + 0x4D2  )/* [0x4D2] */
+#define PULL_CTRL_GP19_SD2_BYTE_ADDR     	(__GPIO_BASE + 0x4D3  )/* [0x4D3] */
+#define PULL_CTRL_GP20_PWM0_BYTE_ADDR      	(__GPIO_BASE + 0x4D4  )/* [0x4D4] */
+#define PULL_CTRL_GP21_HDMI_BYTE_ADDR		(__GPIO_BASE + 0x4D5  )/* [0x4D5] */
+#define PULL_CTRL_GP23_I2C3_BYTE_ADDR		(__GPIO_BASE + 0x4D7  )/* [0x4D7] */
+#define PULL_CTRL_GP24_SF_BYTE_ADDR     	(__GPIO_BASE + 0x4D8  )/* [0x4D8] */
+#define PULL_CTRL_GP26_PCM_BYTE_ADDR		(__GPIO_BASE + 0x4DA  )/* [0x4DA] */
+#define PULL_CTRL_GP27_SD0_BYTE_ADDR		(__GPIO_BASE + 0x4DB  )/* [0x4DB] */
+#define PULL_CTRL_GP60_USB_BYTE_ADDR		(__GPIO_BASE + 0x4FC  )/* [0x4FC] */
+#define PULL_CTRL_GP62_WAKEUP_SUS_BYTE_ADDR	(__GPIO_BASE + 0x4FE  )/* [0x4FE] */
+#define PULL_CTRL_GP63_SD02_BYTE_ADDR		(__GPIO_BASE + 0x4FF  )/* [0x4FF] */
+#define DRV_GPIO_7_0_4BYTE_ADDR				(__GPIO_BASE + 0x800  )/* [0x800 ~ 0x803] */
+#define DRV_GPIO_13_8_4BYTE_ADDR			(__GPIO_BASE + 0x804  )/* [0x804 ~ 0x807] */
+#define DRV_GPIO_19_14_4BYTE_ADDR			(__GPIO_BASE + 0x808  )/* [0x808 ~ 0x80B] */
+#define DRV_VDIN_3_0_4BYTE_ADDR				(__GPIO_BASE + 0x80C  )/* [0x80C ~ 0x80F] */
+#define DRV_VDIN_4_6_4BYTE_ADDR				(__GPIO_BASE + 0x810  )/* [0x810 ~ 0x813] */
+#define DRV_VDIN_SPI_4BYTE_ADDR				(__GPIO_BASE + 0x814  )/* [0x814 ~ 0x817] */
+#define DRV_SPI_NAND_4BYTE_ADDR				(__GPIO_BASE + 0x818  )/* [0x818 ~ 0x81B] */
+#define DRV_NAND_4BYTE_ADDR					(__GPIO_BASE + 0x81C  )/* [0x81C ~ 0x81F] */
+#define DRV_NANDIO_4BYTE_ADDR				(__GPIO_BASE + 0x820  )/* [0x820 ~ 0x823] */
+#define DRV_HDMI_I2C_4BYTE_ADDR				(__GPIO_BASE + 0x824  )/* [0x824 ~ 0x827] */
+#define DRV_I2C_SD0_4BYTE_ADDR				(__GPIO_BASE + 0x828  )/* [0x828 ~ 0x82B] */
+#define DRV_SD0_SD2_4BYTE_ADDR				(__GPIO_BASE + 0x82C  )/* [0x82C ~ 0x82F] */
+#define DRV_SD2_I2S_4BYTE_ADDR				(__GPIO_BASE + 0x830  )/* [0x830 ~ 0x833] */
+#define DRV_I2S_UART_4BYTE_ADDR				(__GPIO_BASE + 0x834  )/* [0x834 ~ 0x837] */
+#define DRV_UART_4BYTE_ADDR					(__GPIO_BASE + 0x838  )/* [0x838 ~ 0x83B] */
+#define DRV_SF_JTAGT_4BYTE_ADDR				(__GPIO_BASE + 0x83C  )/* [0x83C ~ 0x83F] */
+#define DRV_JTAGT_PWM_4BYTE_ADDR			(__GPIO_BASE + 0x840  )/* [0x840 ~ 0x843] */
+#define DRV_PCM_BYTE_ADDR					(__GPIO_BASE + 0x844  )/* [0x844] */
+#define DRV_SPI_BYTE_ADDR					(__GPIO_BASE + 0x84C  )/* [0x84C] */
+
+
+
+#define GPIO_ID_GP0_BYTE_REG					REG8_PTR(GPIO_ID_GP0_BYTE_ADDR )
+#define GPIO_ID_GP1_BYTE_REG 					REG8_PTR(GPIO_ID_GP1_BYTE_ADDR )
+#define GPIO_ID_GP2_BYTE_REG					REG8_PTR(GPIO_ID_GP2_BYTE_ADDR )
+#define GPIO_ID_GP4_VDOUT_7_0_BYTE_REG			REG8_PTR(GPIO_ID_GP4_VDOUT_7_0_BYTE_ADDR )
+#define GPIO_ID_GP5_VDOUT_15_8_BYTE_REG			REG8_PTR(GPIO_ID_GP5_VDOUT_15_8_BYTE_ADDR )
+#define GPIO_ID_GP6_VDOUT_23_16_BYTE_REG		REG8_PTR(GPIO_ID_GP6_VDOUT_23_16_BYTE_ADDR )
+#define GPIO_ID_GP7_VD_BYTE_REG					REG8_PTR(GPIO_ID_GP7_VD_BYTE_ADDR )
+#define GPIO_ID_GP8_VDIN_BYTE_REG				REG8_PTR(GPIO_ID_GP8_VDIN_BYTE_ADDR )
+#define GPIO_ID_GP9_VSYNC_BYTE_REG				REG8_PTR(GPIO_ID_GP9_VSYNC_BYTE_ADDR )
+#define GPIO_ID_GP10_I2S_BYTE_REG				REG8_PTR(GPIO_ID_GP10_I2S_BYTE_ADDR )
+#define GPIO_ID_GP11_I2S_BYTE_REG				REG8_PTR(GPIO_ID_GP11_I2S_BYTE_ADDR )
+#define GPIO_ID_GP12_SPI_BYTE_REG				REG8_PTR(GPIO_ID_GP12_SPI_BYTE_ADDR )
+#define GPIO_ID_GP13_SD0_BYTE_REG   		REG8_PTR(GPIO_ID_GP13_SD0_BYTE_ADDR )
+#define GPIO_ID_GP14_NAND_SD1_BYTE_REG			REG8_PTR(GPIO_ID_GP14_NAND_SD1_BYTE_ADDR )
+#define GPIO_ID_GP15_NAND_BYTE_REG				REG8_PTR(GPIO_ID_GP15_NAND_BYTE_ADDR )
+#define GPIO_ID_GP16_NAND_SD1_BYTE_REG			REG8_PTR(GPIO_ID_GP16_NAND_SD1_BYTE_ADDR )
+#define GPIO_ID_GP17_I2C_BYTE_REG       		REG8_PTR(GPIO_ID_GP17_I2C_BYTE_ADDR )
+#define GPIO_ID_GP18_UART_BYTE_REG				REG8_PTR(GPIO_ID_GP18_UART_BYTE_ADDR )
+#define GPIO_ID_GP19_SD2_BYTE_REG   	    	REG8_PTR(GPIO_ID_GP19_SD2_BYTE_ADDR )
+#define GPIO_ID_GP20_PWM0_BYTE_REG       		REG8_PTR(GPIO_ID_GP20_PWM0_BYTE_ADDR )
+#define GPIO_ID_GP21_HDMI_BYTE_REG       		REG8_PTR(GPIO_ID_GP21_HDMI_BYTE_ADDR )
+#define GPIO_ID_GP23_I2C3_BYTE_REG	    	   	REG8_PTR(GPIO_ID_GP23_I2C3_BYTE_ADDR )
+#define GPIO_ID_GP24_SF_BYTE_REG				REG8_PTR(GPIO_ID_GP24_SF_BYTE_ADDR )
+#define GPIO_ID_GP26_PCM_BYTE_REG       		REG8_PTR(GPIO_ID_GP26_PCM_BYTE_ADDR )
+#define GPIO_ID_GP60_USB_BYTE_REG				REG8_PTR(GPIO_ID_GP60_USB_BYTE_ADDR )
+#define GPIO_ID_GP62_WAKEUP_SUS_BYTE_REG		REG8_PTR(GPIO_ID_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define GPIO_ID_GP63_SD02CD_BYTE_REG			REG8_PTR(GPIO_ID_GP63_SD02CD_BYTE_ADDR )
+#define GPIO_CTRL_GP0_BYTE_REG 					REG8_PTR(GPIO_CTRL_GP0_BYTE_ADDR )
+#define GPIO_CTRL_GP1_BYTE_REG 					REG8_PTR(GPIO_CTRL_GP1_BYTE_ADDR )
+#define GPIO_CTRL_GP2_BYTE_REG 					REG8_PTR(GPIO_CTRL_GP2_BYTE_ADDR )
+#define GPIO_CTRL_GP4_VDOUT_7_0_BYTE_REG		REG8_PTR(GPIO_CTRL_GP4_VDOUT_7_0_BYTE_ADDR )
+#define GPIO_CTRL_GP5_VDOUT_15_8_BYTE_REG		REG8_PTR(GPIO_CTRL_GP5_VDOUT_15_8_BYTE_ADDR )
+#define GPIO_CTRL_GP6_VDOUT_23_16_BYTE_REG		REG8_PTR(GPIO_CTRL_GP6_VDOUT_23_16_BYTE_ADDR )
+#define GPIO_CTRL_GP7_VD_BYTE_REG				REG8_PTR(GPIO_CTRL_GP7_VD_BYTE_ADDR )
+#define GPIO_CTRL_GP8_VDIN_BYTE_REG				REG8_PTR(GPIO_CTRL_GP8_VDIN_BYTE_ADDR )
+#define GPIO_CTRL_GP9_VSYNC_BYTE_REG 			REG8_PTR(GPIO_CTRL_GP9_VSYNC_BYTE_ADDR )
+#define GPIO_CTRL_GP10_I2S_BYTE_REG				REG8_PTR(GPIO_CTRL_GP10_I2S_BYTE_ADDR )
+#define GPIO_CTRL_GP11_I2S_BYTE_REG      		REG8_PTR(GPIO_CTRL_GP11_I2S_BYTE_ADDR )
+#define GPIO_CTRL_GP12_SPI_BYTE_REG				REG8_PTR(GPIO_CTRL_GP12_SPI_BYTE_ADDR )
+#define GPIO_CTRL_GP13_SD0_BYTE_REG       	REG8_PTR(GPIO_CTRL_GP13_SD0_BYTE_ADDR )
+#define GPIO_CTRL_GP14_NAND_SD1_BYTE_REG		REG8_PTR(GPIO_CTRL_GP14_NAND_SD1_BYTE_ADDR )
+#define GPIO_CTRL_GP15_NAND_BYTE_REG			REG8_PTR(GPIO_CTRL_GP15_NAND_BYTE_ADDR )
+#define GPIO_CTRL_GP16_NAND_SD1_BYTE_REG		REG8_PTR(GPIO_CTRL_GP16_NAND_SD1_BYTE_ADDR )
+#define GPIO_CTRL_GP17_I2C_BYTE_REG       		REG8_PTR(GPIO_CTRL_GP17_I2C_BYTE_ADDR )
+#define GPIO_CTRL_GP18_UART_BYTE_REG			REG8_PTR(GPIO_CTRL_GP18_UART_BYTE_ADDR )
+#define GPIO_CTRL_GP19_SD2_BYTE_REG   	    	REG8_PTR(GPIO_CTRL_GP19_SD2_BYTE_ADDR )
+#define GPIO_CTRL_GP20_PWM0_BYTE_REG       		REG8_PTR(GPIO_CTRL_GP20_PWM0_BYTE_ADDR )
+#define GPIO_CTRL_GP21_HDMI_BYTE_REG       		REG8_PTR(GPIO_CTRL_GP21_HDMI_BYTE_ADDR )
+#define GPIO_CTRL_GP23_I2C3_BYTE_REG	    	REG8_PTR(GPIO_CTRL_GP23_I2C3_BYTE_ADDR )
+#define GPIO_CTRL_GP24_SF_BYTE_REG				REG8_PTR(GPIO_CTRL_GP24_SF_BYTE_ADDR )
+#define GPIO_CTRL_GP26_PCM_BYTE_REG       		REG8_PTR(GPIO_CTRL_GP26_PCM_BYTE_ADDR )
+#define GPIO_CTRL_GP60_USB_BYTE_REG				REG8_PTR(GPIO_CTRL_GP60_USB_BYTE_ADDR )
+#define GPIO_CTRL_GP62_WAKEUP_SUS_BYTE_REG		REG8_PTR(GPIO_CTRL_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define GPIO_CTRL_GP63_SD02CD_BYTE_REG			REG8_PTR(GPIO_CTRL_GP63_SD02CD_BYTE_ADDR )
+#define GPIO_OC_GP0_BYTE_REG 					REG8_PTR(GPIO_OC_GP0_BYTE_ADDR )
+#define GPIO_OC_GP1_BYTE_REG 					REG8_PTR(GPIO_OC_GP1_BYTE_ADDR )
+#define GPIO_OC_GP2_BYTE_REG					REG8_PTR(GPIO_OC_GP2_BYTE_ADDR )
+#define GPIO_OC_GP4_VDOUT_7_0_BYTE_REG			REG8_PTR(GPIO_OC_GP4_VDOUT_7_0_BYTE_ADDR )
+#define GPIO_OC_GP5_VDOUT_15_8_BYTE_REG			REG8_PTR(GPIO_OC_GP5_VDOUT_15_8_BYTE_ADDR )
+#define GPIO_OC_GP6_VDOUT_23_16_BYTE_REG		REG8_PTR(GPIO_OC_GP6_VDOUT_23_16_BYTE_ADDR )
+#define GPIO_OC_GP7_VD_BYTE_REG					REG8_PTR(GPIO_OC_GP7_VD_BYTE_ADDR )
+#define GPIO_OC_GP8_VDIN_BYTE_REG				REG8_PTR(GPIO_OC_GP8_VDIN_BYTE_ADDR )
+#define GPIO_OC_GP9_VSYNC_BYTE_REG 				REG8_PTR(GPIO_OC_GP9_VSYNC_BYTE_ADDR )
+#define GPIO_OC_GP10_I2S_BYTE_REG				REG8_PTR(GPIO_OC_GP10_I2S_BYTE_ADDR )
+#define GPIO_OC_GP11_I2S_BYTE_REG      			REG8_PTR(GPIO_OC_GP11_I2S_BYTE_ADDR )
+#define GPIO_OC_GP12_SPI_BYTE_REG				REG8_PTR(GPIO_OC_GP12_SPI_BYTE_ADDR )
+#define GPIO_OC_GP13_SD0_BYTE_REG   		REG8_PTR(GPIO_OC_GP13_SD0_BYTE_ADDR )
+#define GPIO_OC_GP14_NAND_SD1_BYTE_REG			REG8_PTR(GPIO_OC_GP14_NAND_SD1_BYTE_ADDR )
+#define GPIO_OC_GP15_NAND_BYTE_REG				REG8_PTR(GPIO_OC_GP15_NAND_BYTE_ADDR )
+#define GPIO_OC_GP16_NAND_SD1_BYTE_REG			REG8_PTR(GPIO_OC_GP16_NAND_SD1_BYTE_ADDR )
+#define GPIO_OC_GP17_I2C_BYTE_REG       		REG8_PTR(GPIO_OC_GP17_I2C_BYTE_ADDR )
+#define GPIO_OC_GP18_UART_BYTE_REG				REG8_PTR(GPIO_OC_GP18_UART_BYTE_ADDR )
+#define GPIO_OC_GP19_SD2_BYTE_REG   	    	REG8_PTR(GPIO_OC_GP19_SD2_BYTE_ADDR )
+#define GPIO_OC_GP20_PWM0_BYTE_REG       		REG8_PTR(GPIO_OC_GP20_PWM0_BYTE_ADDR )
+#define GPIO_OC_GP21_HDMI_BYTE_REG       		REG8_PTR(GPIO_OC_GP21_HDMI_BYTE_ADDR )
+#define GPIO_OC_GP22_I2C3_BYTE_REG	     	  	REG8_PTR(GPIO_OC_GP22_I2C3_BYTE_ADDR )
+#define GPIO_OC_GP24_SF_BYTE_REG				REG8_PTR(GPIO_OC_GP24_SF_BYTE_ADDR )
+#define GPIO_OC_GP26_PCM_BYTE_REG       		REG8_PTR(GPIO_OC_GP26_PCM_BYTE_ADDR )
+#define GPIO_OC_GP60_USB_BYTE_REG				REG8_PTR(GPIO_OC_GP60_USB_BYTE_ADDR )
+#define GPIO_OC_GP62_WAKEUP_SUS_BYTE_REG		REG8_PTR(GPIO_OC_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define GPIO_OC_GP63_SD02CD_BYTE_REG			REG8_PTR(GPIO_OC_GP63_SD02CD_BYTE_ADDR )
+#define GPIO_OD_GP0_BYTE_REG 					REG8_PTR(GPIO_OD_GP0_BYTE_ADDR )
+#define GPIO_OD_GP1_BYTE_REG 					REG8_PTR(GPIO_OD_GP1_BYTE_ADDR )
+#define GPIO_OD_GP2_BYTE_REG					REG8_PTR(GPIO_OD_GP2_BYTE_ADDR )
+#define GPIO_OD_GP4_VDOUT_7_0_BYTE_REG			REG8_PTR(GPIO_OD_GP4_VDOUT_7_0_BYTE_ADDR )
+#define GPIO_OD_GP5_VDOUT_15_8_BYTE_REG			REG8_PTR(GPIO_OD_GP5_VDOUT_15_8_BYTE_ADDR )
+#define GPIO_OD_GP6_VDOUT_23_16_BYTE_REG		REG8_PTR(GPIO_OD_GP6_VDOUT_23_16_BYTE_ADDR )
+#define GPIO_OD_GP7_VD_BYTE_REG					REG8_PTR(GPIO_OD_GP7_VD_BYTE_ADDR )
+#define GPIO_OD_GP8_VDIN_BYTE_REG				REG8_PTR(GPIO_OD_GP8_VDIN_BYTE_ADDR )
+#define GPIO_OD_GP9_VSYNC_BYTE_REG 				REG8_PTR(GPIO_OD_GP9_VSYNC_BYTE_ADDR )
+#define GPIO_OD_GP10_I2S_BYTE_REG				REG8_PTR(GPIO_OD_GP10_I2S_BYTE_ADDR )
+#define GPIO_OD_GP11_I2S_BYTE_REG      			REG8_PTR(GPIO_OD_GP11_I2S_BYTE_ADDR )
+#define GPIO_OD_GP12_SPI_BYTE_REG				REG8_PTR(GPIO_OD_GP12_SPI_BYTE_ADDR )
+#define GPIO_OD_GP13_SD0_BYTE_REG   		REG8_PTR(GPIO_OD_GP13_SD0_BYTE_ADDR )
+#define GPIO_OD_GP14_NAND_SD1_BYTE_REG			REG8_PTR(GPIO_OD_GP14_NAND_SD1_BYTE_ADDR )
+#define GPIO_OD_GP15_NAND_BYTE_REG				REG8_PTR(GPIO_OD_GP15_NAND_BYTE_ADDR )
+#define GPIO_OD_GP16_NAND_SD1_BYTE_REG			REG8_PTR(GPIO_OD_GP16_NAND_SD1_BYTE_ADDR )
+#define GPIO_OD_GP17_I2C_BYTE_REG       		REG8_PTR(GPIO_OD_GP17_I2C_BYTE_ADDR )
+#define GPIO_OD_GP18_UART_BYTE_REG				REG8_PTR(GPIO_OD_GP18_UART_BYTE_ADDR )
+#define GPIO_OD_GP19_SD2_BYTE_REG   	    	REG8_PTR(GPIO_OD_GP19_SD2_BYTE_ADDR )
+#define GPIO_OD_GP20_PWM0_BYTE_REG       		REG8_PTR(GPIO_OD_GP20_PWM0_BYTE_ADDR )
+#define GPIO_OD_GP21_HDMI_BYTE_REG       		REG8_PTR(GPIO_OD_GP21_HDMI_BYTE_ADDR )
+#define GPIO_OD_GP23_I2C3_BYTE_REG	       		REG8_PTR(GPIO_OD_GP23_I2C3_BYTE_ADDR )
+#define GPIO_OD_GP24_SF_BYTE_REG				REG8_PTR(GPIO_OD_GP24_SF_BYTE_ADDR )
+#define GPIO_OD_GP26_PCM_BYTE_REG       		REG8_PTR(GPIO_OD_GP26_PCM_BYTE_ADDR )
+#define GPIO_OD_GP60_USB_BYTE_REG				REG8_PTR(GPIO_OD_GP60_USB_BYTE_ADDR )
+#define GPIO_OD_GP62_WAKEUP_SUS_BYTE_REG		REG8_PTR(GPIO_OD_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define GPIO_OD_GP63_SD02CD_BYTE_REG			REG8_PTR(GPIO_OD_GP63_SD02CD_BYTE_ADDR )
+#define STRAP_STATUS_REG					REG32_PTR(STRAP_STATUS_ADDR )
+#define AHB_CTRL_4BYTE_REG 					REG32_PTR(AHB_CTRL_4BYTE_ADDR )
+#define USB_OP_CTRL_4BYTE_REG				REG32_PTR(USB_OP_CTRL_4BYTE_ADDR )
+#define BONDING_OPTION_4BYTE_REG			REG32_PTR(BONDING_OPTION_4BYTE_ADDR )
+#define PIN_SHARING_SEL_4BYTE_REG 			REG32_PTR(PIN_SHARING_SEL_4BYTE_ADDR )
+#define TPIU_CLK_DATA_4BYTE_REG 			REG32_PTR(TPIU_CLK_DATA_4BYTE_ADDR )
+#define GPIO0_INT_REQ_TYPE_REG				REG8_PTR(GPIO0_INT_REQ_TYPE_ADDR )
+#define GPIO1_INT_REQ_TYPE_REG				REG8_PTR(GPIO1_INT_REQ_TYPE_ADDR )
+#define GPIO2_INT_REQ_TYPE_REG				REG8_PTR(GPIO2_INT_REQ_TYPE_ADDR )
+#define GPIO3_INT_REQ_TYPE_REG				REG8_PTR(GPIO3_INT_REQ_TYPE_ADDR )
+#define GPIO4_INT_REQ_TYPE_REG				REG8_PTR(GPIO4_INT_REQ_TYPE_ADDR )
+#define GPIO5_INT_REQ_TYPE_REG				REG8_PTR(GPIO5_INT_REQ_TYPE_ADDR )
+#define GPIO6_INT_REQ_TYPE_REG				REG8_PTR(GPIO6_INT_REQ_TYPE_ADDR )
+#define GPIO7_INT_REQ_TYPE_REG				REG8_PTR(GPIO7_INT_REQ_TYPE_ADDR )
+#define GPIO8_INT_REQ_TYPE_REG				REG8_PTR(GPIO8_INT_REQ_TYPE_ADDR )
+#define GPIO9_INT_REQ_TYPE_REG				REG8_PTR(GPIO9_INT_REQ_TYPE_ADDR )
+#define GPIO10_INT_REQ_TYPE_REG				REG8_PTR(GPIO10_INT_REQ_TYPE_ADDR )
+#define GPIO11_INT_REQ_TYPE_REG				REG8_PTR(GPIO11_INT_REQ_TYPE_ADDR )
+#define GPIO12_INT_REQ_TYPE_REG				REG8_PTR(GPIO12_INT_REQ_TYPE_ADDR )
+#define GPIO13_INT_REQ_TYPE_REG				REG8_PTR(GPIO13_INT_REQ_TYPE_ADDR )
+#define GPIO18_INT_REQ_TYPE_REG				REG8_PTR(GPIO18_INT_REQ_TYPE_ADDR )
+#define GPIO19_INT_REQ_TYPE_REG				REG8_PTR(GPIO19_INT_REQ_TYPE_ADDR )
+#define VOUT20_INT_REQ_TYPE_REG				REG8_PTR(VOUT20_INT_REQ_TYPE_ADDR )
+#define VOUT21_INT_REQ_TYPE_REG				REG8_PTR(VOUT21_INT_REQ_TYPE_ADDR )
+#define VOUT22_INT_REQ_TYPE_REG				REG8_PTR(VOUT22_INT_REQ_TYPE_ADDR )
+#define VOUT23_INT_REQ_TYPE_REG				REG8_PTR(VOUT23_INT_REQ_TYPE_ADDR )
+#define GPIO20_INT_REQ_TYPE_REG				REG8_PTR(GPIO20_INT_REQ_TYPE_ADDR )
+#define GPIO21_INT_REQ_TYPE_REG				REG8_PTR(GPIO21_INT_REQ_TYPE_ADDR )
+#define GPIO22_INT_REQ_TYPE_REG				REG8_PTR(GPIO22_INT_REQ_TYPE_ADDR )
+#define GPIO23_INT_REQ_TYPE_REG				REG8_PTR(GPIO23_INT_REQ_TYPE_ADDR )
+#define GPIO24_INT_REQ_TYPE_REG				REG8_PTR(GPIO24_INT_REQ_TYPE_ADDR )
+#define GPIO25_INT_REQ_TYPE_REG				REG8_PTR(GPIO25_INT_REQ_TYPE_ADDR )
+#define GPIO0_INT_REQ_STS_REG				REG8_PTR(GPIO0_INT_REQ_STS_ADDR )
+#define GPIO1_INT_REQ_STS_REG				REG8_PTR(GPIO1_INT_REQ_STS_ADDR )
+#define GPIO2_INT_REQ_STS_REG				REG8_PTR(GPIO2_INT_REQ_STS_ADDR )
+#define GPIO3_INT_REQ_STS_REG				REG8_PTR(GPIO3_INT_REQ_STS_ADDR )
+#define DRV_DVO_CLK_BYTE_REG				REG8_PTR(DRV_DVO_CLK_BYTE_ADDR )
+#define DRV_DVO_VDEN_BYTE_REG				REG8_PTR(DRV_DVO_VDEN_BYTE_ADDR )
+#define SD0_DPCTL_4BYTE_REG					REG32_PTR(SD0_DPCTL_4BYTE_ADDR )
+#define SD0_DNCTL_4BYTE_REG					REG32_PTR(SD0_DNCTL_4BYTE_ADDR )
+#define DRV_SD0_USB_BYTE_REG				REG8_PTR(DRV_SD0_USB_BYTE_ADDR )	
+#define DRV_USB_SWOC0_BYTE_REG				REG8_PTR(DRV_USB_SWOC0_BYTE_ADDR )
+#define DRV_USB_OC12_BYTE_REG				REG8_PTR(DRV_USB_OC12_BYTE_ADDR )
+#define DRV_USBOC3_CIR_BYTE_REG				REG8_PTR(DRV_USBOC3_CIR_BYTE_ADDR )
+#define DRV_PWREN_BYTE_REG					REG8_PTR(DRV_PWREN_BYTE_ADDR )
+#define DRV_PWREN_WAKEUP0_BYTE_REG			REG8_PTR(DRV_PWREN_WAKEUP0_BYTE_ADDR )
+#define DRV_SUSGP01_BYTE_REG				REG8_PTR(DRV_SUSGP01_BYTE_ADDR )
+#define DRV_WAKEUP23_BYTE_REG				REG8_PTR(DRV_WAKEUP23_BYTE_ADDR )
+#define DRV_WAKEUP45_BYTE_REG				REG8_PTR(DRV_WAKEUP45_BYTE_ADDR )
+#define DRV_I2C_BYTE_REG					REG8_PTR(DRV_I2C_BYTE_ADDR )
+#define DRV_HDMI_BYTE_REG					REG8_PTR(DRV_HDMI_BYTE_ADDR )	
+#define PULL_EN_GP0_BYTE_REG				REG8_PTR(PULL_EN_GP0_BYTE_ADDR )
+#define PULL_EN_GP1_BYTE_REG				REG8_PTR(PULL_EN_GP1_BYTE_ADDR )
+#define PULL_EN_GP2_BYTE_REG				REG8_PTR(PULL_EN_GP2_BYTE_ADDR )
+#define PULL_EN_GP4_VDOUT_7_0_BYTE_REG		REG8_PTR(PULL_EN_GP4_VDOUT_7_0_BYTE_ADDR )
+#define PULL_EN_GP5_VDOUT_15_8_BYTE_REG		REG8_PTR(PULL_EN_GP5_VDOUT_15_8_BYTE_ADDR )
+#define PULL_EN_GP6_VDOUT_23_16_BYTE_REG	REG8_PTR(PULL_EN_GP6_VDOUT_23_16_BYTE_ADDR )
+#define PULL_EN_GP7_VD_BYTE_REG     		REG8_PTR(PULL_EN_GP7_VD_BYTE_ADDR )
+#define PULL_EN_GP8_VDIN_BYTE_REG   		REG8_PTR(PULL_EN_GP8_VDIN_BYTE_ADDR )
+#define PULL_EN_GP9_VSYNC_BYTE_REG 			REG8_PTR(PULL_EN_GP9_VSYNC_BYTE_ADDR )
+#define PULL_EN_GP10_I2S_BYTE_REG 			REG8_PTR(PULL_EN_GP10_I2S_BYTE_ADDR )
+#define PULL_EN_GP11_I2S_BYTE_REG     		REG8_PTR(PULL_EN_GP11_I2S_BYTE_ADDR )
+#define PULL_EN_GP12_SPI_BYTE_REG			REG8_PTR(PULL_EN_GP12_SPI_BYTE_ADDR )
+#define PULL_EN_GP13_SD0_BYTE_REG       	REG8_PTR(PULL_EN_GP13_SD0_BYTE_ADDR )
+#define PULL_EN_GP14_NAND_BYTE_REG      	REG8_PTR(PULL_EN_GP14_NAND_BYTE_ADDR )
+#define PULL_EN_GP15_NAND_BYTE_REG			REG8_PTR(PULL_EN_GP15_NAND_BYTE_ADDR )
+#define PULL_EN_GP16_NANDIO_BYTE_REG		REG8_PTR(PULL_EN_GP16_NANDIO_BYTE_ADDR )
+#define PULL_EN_GP17_I2C_BYTE_REG			REG8_PTR(PULL_EN_GP17_I2C_BYTE_ADDR )
+#define PULL_EN_GP18_UART_BYTE_REG			REG8_PTR(PULL_EN_GP18_UART_BYTE_ADDR )
+#define PULL_EN_GP19_SD2_BYTE_REG			REG8_PTR(PULL_EN_GP19_SD2_BYTE_ADDR )
+#define PULL_EN_GP20_PWM0_BYTE_REG			REG8_PTR(PULL_EN_GP20_PWM0_BYTE_ADDR )
+#define PULL_EN_GP21_HDMI_BYTE_REG      	REG8_PTR(PULL_EN_GP21_HDMI_BYTE_ADDR )
+#define PULL_EN_GP23_I2C3_BYTE_REG			REG8_PTR(PULL_EN_GP23_I2C3_BYTE_ADDR )
+#define PULL_EN_GP24_SF_BYTE_REG			REG8_PTR(PULL_EN_GP24_SF_BYTE_ADDR )
+#define PULL_EN_GP26_PCM_BYTE_REG			REG8_PTR(PULL_EN_GP26_PCM_BYTE_ADDR )
+#define PULL_EN_GP60_USB_BYTE_REG			REG8_PTR(PULL_EN_GP60_USB_BYTE_ADDR )
+#define PULL_EN_GP62_WAKEUP_SUS_BYTE_REG	REG8_PTR(PULL_EN_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define PULL_EN_GP63_SD02_BYTE_REG			REG8_PTR(PULL_EN_GP63_SD02_BYTE_ADDR )
+#define PULL_CTRL_GP0_BYTE_REG				REG8_PTR(PULL_CTRL_GP0_BYTE_ADDR )
+#define PULL_CTRL_GP1_BYTE_REG				REG8_PTR(PULL_CTRL_GP1_BYTE_ADDR )
+#define PULL_CTRL_GP2_BYTE_REG				REG8_PTR(PULL_CTRL_GP2_BYTE_ADDR )
+#define PULL_CTRL_GP4_VDOUT_7_0_BYTE_REG	REG8_PTR(PULL_CTRL_GP4_VDOUT_7_0_BYTE_ADDR )
+#define PULL_CTRL_GP5_VDOUT_15_8_BYTE_REG	REG8_PTR(PULL_CTRL_GP5_VDOUT_15_8_BYTE_ADDR )
+#define PULL_CTRL_GP6_VDOUT_23_16_BYTE_REG	REG8_PTR(PULL_CTRL_GP6_VDOUT_23_16_BYTE_ADDR )
+#define PULL_CTRL_GP7_VD_BYTE_REG			REG8_PTR(PULL_CTRL_GP7_VD_BYTE_ADDR )
+#define PULL_CTRL_GP8_VDIN_BYTE_REG			REG8_PTR(PULL_CTRL_GP8_VDIN_BYTE_ADDR )
+#define PULL_CTRL_GP9_VSYNC_BYTE_REG		REG8_PTR(PULL_CTRL_GP9_VSYNC_BYTE_ADDR )
+#define PULL_CTRL_GP10_I2S_BYTE_REG			REG8_PTR(PULL_CTRL_GP10_I2S_BYTE_ADDR )
+#define PULL_CTRL_GP11_I2S_BYTE_REG			REG8_PTR(PULL_CTRL_GP11_I2S_BYTE_ADDR )
+#define PULL_CTRL_GP12_SPI_BYTE_REG			REG8_PTR(PULL_CTRL_GP12_SPI_BYTE_ADDR )
+#define PULL_CTRL_GP13_SD0_BYTE_REG			REG8_PTR(PULL_CTRL_GP13_SD0_BYTE_ADDR )
+#define PULL_CTRL_GP14_NAND_BYTE_REG       	REG8_PTR(PULL_CTRL_GP14_NAND_BYTE_ADDR )
+#define PULL_CTRL_GP15_NAND_BYTE_REG		REG8_PTR(PULL_CTRL_GP15_NAND_BYTE_ADDR )
+#define PULL_CTRL_GP16_NANDIO_BYTE_REG		REG8_PTR(PULL_CTRL_GP16_NANDIO_BYTE_ADDR )
+#define PULL_CTRL_GP17_I2C_BYTE_REG     	REG8_PTR(PULL_CTRL_GP17_I2C_BYTE_ADDR )
+#define PULL_CTRL_GP18_UART_BYTE_REG     	REG8_PTR(PULL_CTRL_GP18_UART_BYTE_ADDR )
+#define PULL_CTRL_GP19_SD2_BYTE_REG     	REG8_PTR(PULL_CTRL_GP19_SD2_BYTE_ADDR )
+#define PULL_CTRL_GP20_PWM0_BYTE_REG      	REG8_PTR(PULL_CTRL_GP20_PWM0_BYTE_ADDR )
+#define PULL_CTRL_GP21_HDMI_BYTE_REG		REG8_PTR(PULL_CTRL_GP21_HDMI_BYTE_ADDR )
+#define PULL_CTRL_GP23_I2C3_BYTE_REG		REG8_PTR(PULL_CTRL_GP23_I2C3_BYTE_ADDR )
+#define PULL_CTRL_GP24_SF_BYTE_REG     		REG8_PTR(PULL_CTRL_GP24_SF_BYTE_ADDR )
+#define PULL_CTRL_GP26_PCM_BYTE_REG			REG8_PTR(PULL_CTRL_GP26_PCM_BYTE_ADDR )
+#define PULL_CTRL_GP27_SD0_BYTE_REG			REG8_PTR(PULL_CTRL_GP27_SD0_BYTE_ADDR )
+#define PULL_CTRL_GP60_USB_BYTE_REG			REG8_PTR(PULL_CTRL_GP60_USB_BYTE_ADDR )
+#define PULL_CTRL_GP62_WAKEUP_SUS_BYTE_REG	REG8_PTR(PULL_CTRL_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define PULL_CTRL_GP63_SD02_BYTE_REG		REG8_PTR(PULL_CTRL_GP63_SD02_BYTE_ADDR )
+#define DRV_GPIO_7_0_4BYTE_REG				REG32_PTR(DRV_GPIO_7_0_4BYTE_ADDR )
+#define DRV_GPIO_13_8_4BYTE_REG				REG32_PTR(DRV_GPIO_13_8_4BYTE_ADDR )
+#define DRV_GPIO_19_14_4BYTE_REG			REG32_PTR(DRV_GPIO_19_14_4BYTE_ADDR )
+#define DRV_VDIN_3_0_4BYTE_REG				REG32_PTR(DRV_VDIN_3_0_4BYTE_ADDR )
+#define DRV_VDIN_4_6_4BYTE_REG				REG32_PTR(DRV_VDIN_3_0_4BYTE_ADDR )
+#define DRV_VDIN_SPI_4BYTE_REG				REG32_PTR(DRV_VDIN_SPI_4BYTE_ADDR )
+#define DRV_SPI_NAND_4BYTE_REG				REG32_PTR(DRV_SPI_NAND_4BYTE_ADDR )
+#define DRV_NAND_4BYTE_REG					REG32_PTR(DRV_NAND_4BYTE_ADDR )
+#define DRV_NANDIO_4BYTE_REG				REG32_PTR(DRV_NANDIO_4BYTE_ADDR )
+#define DRV_HDMI_I2C_4BYTE_REG				REG32_PTR(DRV_HDMI_I2C_4BYTE_ADDR )
+#define DRV_I2C_SD0_4BYTE_REG				REG32_PTR(DRV_I2C_SD0_4BYTE_ADDR )
+#define DRV_SD0_SD2_4BYTE_REG				REG32_PTR(DRV_SD0_SD2_4BYTE_ADDR )
+#define DRV_SD2_I2S_4BYTE_REG				REG32_PTR(DRV_SD2_I2S_4BYTE_ADDR )
+#define DRV_I2S_UART_4BYTE_REG				REG32_PTR(DRV_I2S_UART_4BYTE_ADDR )
+#define DRV_UART_4BYTE_REG					REG32_PTR(DRV_UART_4BYTE_ADDR )
+#define DRV_SF_JTAGT_4BYTE_REG				REG32_PTR(DRV_SF_JTAGT_4BYTE_ADDR )
+#define DRV_JTAGT_PWM_4BYTE_REG				REG32_PTR(DRV_JTAGT_PWM_4BYTE_ADDR )
+#define DRV_PCM_BYTE_REG					REG8_PTR(DRV_PCM_BYTE_ADDR )
+#define DRV_SPI_BYTE_REG					REG8_PTR(DRV_SPI_BYTE_ADDR )
+
+#define GPIO_ID_GP0_BYTE_VAL					REG8_VAL(GPIO_ID_GP0_BYTE_ADDR )
+#define GPIO_ID_GP1_BYTE_VAL 					REG8_VAL(GPIO_ID_GP1_BYTE_ADDR )
+#define GPIO_ID_GP2_BYTE_VAL					REG8_VAL(GPIO_ID_GP2_BYTE_ADDR )
+#define GPIO_ID_GP4_VDOUT_7_0_BYTE_VAL			REG8_VAL(GPIO_ID_GP4_VDOUT_7_0_BYTE_ADDR )
+#define GPIO_ID_GP5_VDOUT_15_8_BYTE_VAL			REG8_VAL(GPIO_ID_GP5_VDOUT_15_8_BYTE_ADDR )
+#define GPIO_ID_GP6_VDOUT_23_16_BYTE_VAL		REG8_VAL(GPIO_ID_GP6_VDOUT_23_16_BYTE_ADDR )
+#define GPIO_ID_GP7_VD_BYTE_VAL					REG8_VAL(GPIO_ID_GP7_VD_BYTE_ADDR )
+#define GPIO_ID_GP8_VDIN_BYTE_VAL				REG8_VAL(GPIO_ID_GP8_VDIN_BYTE_ADDR )
+#define GPIO_ID_GP9_VSYNC_BYTE_VAL				REG8_VAL(GPIO_ID_GP9_VSYNC_BYTE_ADDR )
+#define GPIO_ID_GP10_I2S_BYTE_VAL				REG8_VAL(GPIO_ID_GP10_I2S_BYTE_ADDR )
+#define GPIO_ID_GP11_I2S_BYTE_VAL				REG8_VAL(GPIO_ID_GP11_I2S_BYTE_ADDR )
+#define GPIO_ID_GP12_SPI_BYTE_VAL				REG8_VAL(GPIO_ID_GP12_SPI_BYTE_ADDR )
+#define GPIO_ID_GP13_SD0_BYTE_VAL   		REG8_VAL(GPIO_ID_GP13_SD0_BYTE_ADDR )
+#define GPIO_ID_GP14_NAND_SD1_BYTE_VAL			REG8_VAL(GPIO_ID_GP14_NAND_SD1_BYTE_ADDR )
+#define GPIO_ID_GP15_NAND_BYTE_VAL				REG8_VAL(GPIO_ID_GP15_NAND_BYTE_ADDR )
+#define GPIO_ID_GP16_NAND_SD1_BYTE_VAL			REG8_VAL(GPIO_ID_GP16_NAND_SD1_BYTE_ADDR )
+#define GPIO_ID_GP17_I2C_BYTE_VAL       		REG8_VAL(GPIO_ID_GP17_I2C_BYTE_ADDR )
+#define GPIO_ID_GP18_UART_BYTE_VAL				REG8_VAL(GPIO_ID_GP18_UART_BYTE_ADDR )
+#define GPIO_ID_GP19_SD2_BYTE_VAL   	    	REG8_VAL(GPIO_ID_GP19_SD2_BYTE_ADDR )
+#define GPIO_ID_GP20_PWM0_BYTE_VAL       		REG8_VAL(GPIO_ID_GP20_PWM0_BYTE_ADDR )
+#define GPIO_ID_GP21_HDMI_BYTE_VAL       		REG8_VAL(GPIO_ID_GP21_HDMI_BYTE_ADDR )
+#define GPIO_ID_GP23_I2C3_BYTE_VAL	    	   	REG8_VAL(GPIO_ID_GP23_I2C3_BYTE_ADDR )
+#define GPIO_ID_GP24_SF_BYTE_VAL				REG8_VAL(GPIO_ID_GP24_SF_BYTE_ADDR )
+#define GPIO_ID_GP26_PCM_BYTE_VAL       		REG8_VAL(GPIO_ID_GP26_PCM_BYTE_ADDR )
+#define GPIO_ID_GP60_USB_BYTE_VAL				REG8_VAL(GPIO_ID_GP60_USB_BYTE_ADDR )
+#define GPIO_ID_GP62_WAKEUP_SUS_BYTE_VAL		REG8_VAL(GPIO_ID_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define GPIO_ID_GP63_SD02CD_BYTE_VAL			REG8_VAL(GPIO_ID_GP63_SD02CD_BYTE_ADDR )
+#define GPIO_CTRL_GP0_BYTE_VAL 					REG8_VAL(GPIO_CTRL_GP0_BYTE_ADDR )
+#define GPIO_CTRL_GP1_BYTE_VAL 					REG8_VAL(GPIO_CTRL_GP1_BYTE_ADDR )
+#define GPIO_CTRL_GP2_BYTE_VAL 					REG8_VAL(GPIO_CTRL_GP2_BYTE_ADDR )
+#define GPIO_CTRL_GP4_VDOUT_7_0_BYTE_VAL		REG8_VAL(GPIO_CTRL_GP4_VDOUT_7_0_BYTE_ADDR )
+#define GPIO_CTRL_GP5_VDOUT_15_8_BYTE_VAL		REG8_VAL(GPIO_CTRL_GP5_VDOUT_15_8_BYTE_ADDR )
+#define GPIO_CTRL_GP6_VDOUT_23_16_BYTE_VAL		REG8_VAL(GPIO_CTRL_GP6_VDOUT_23_16_BYTE_ADDR )
+#define GPIO_CTRL_GP7_VD_BYTE_VAL				REG8_VAL(GPIO_CTRL_GP7_VD_BYTE_ADDR )
+#define GPIO_CTRL_GP8_VDIN_BYTE_VAL				REG8_VAL(GPIO_CTRL_GP8_VDIN_BYTE_ADDR )
+#define GPIO_CTRL_GP9_VSYNC_BYTE_VAL 			REG8_VAL(GPIO_CTRL_GP9_VSYNC_BYTE_ADDR )
+#define GPIO_CTRL_GP10_I2S_BYTE_VAL				REG8_VAL(GPIO_CTRL_GP10_I2S_BYTE_ADDR )
+#define GPIO_CTRL_GP11_I2S_BYTE_VAL      		REG8_VAL(GPIO_CTRL_GP11_I2S_BYTE_ADDR )
+#define GPIO_CTRL_GP12_SPI_BYTE_VAL				REG8_VAL(GPIO_CTRL_GP12_SPI_BYTE_ADDR )
+#define GPIO_CTRL_GP13_SD0_BYTE_VAL       	REG8_VAL(GPIO_CTRL_GP13_SD0_BYTE_ADDR )
+#define GPIO_CTRL_GP14_NAND_SD1_BYTE_VAL		REG8_VAL(GPIO_CTRL_GP14_NAND_SD1_BYTE_ADDR )
+#define GPIO_CTRL_GP15_NAND_BYTE_VAL			REG8_VAL(GPIO_CTRL_GP15_NAND_BYTE_ADDR )
+#define GPIO_CTRL_GP16_NAND_SD1_BYTE_VAL		REG8_VAL(GPIO_CTRL_GP16_NAND_SD1_BYTE_ADDR )
+#define GPIO_CTRL_GP17_I2C_BYTE_VAL       		REG8_VAL(GPIO_CTRL_GP17_I2C_BYTE_ADDR )
+#define GPIO_CTRL_GP18_UART_BYTE_VAL			REG8_VAL(GPIO_CTRL_GP18_UART_BYTE_ADDR )
+#define GPIO_CTRL_GP19_SD2_BYTE_VAL   	    	REG8_VAL(GPIO_CTRL_GP19_SD2_BYTE_ADDR )
+#define GPIO_CTRL_GP20_PWM0_BYTE_VAL       		REG8_VAL(GPIO_CTRL_GP20_PWM0_BYTE_ADDR )
+#define GPIO_CTRL_GP21_HDMI_BYTE_VAL       		REG8_VAL(GPIO_CTRL_GP21_HDMI_BYTE_ADDR )
+#define GPIO_CTRL_GP23_I2C3_BYTE_VAL	    	REG8_VAL(GPIO_CTRL_GP23_I2C3_BYTE_ADDR )
+#define GPIO_CTRL_GP24_SF_BYTE_VAL				REG8_VAL(GPIO_CTRL_GP24_SF_BYTE_ADDR )
+#define GPIO_CTRL_GP26_PCM_BYTE_VAL       		REG8_VAL(GPIO_CTRL_GP26_PCM_BYTE_ADDR )
+#define GPIO_CTRL_GP60_USB_BYTE_VAL				REG8_VAL(GPIO_CTRL_GP60_USB_BYTE_ADDR )
+#define GPIO_CTRL_GP62_WAKEUP_SUS_BYTE_VAL		REG8_VAL(GPIO_CTRL_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define GPIO_CTRL_GP63_SD02CD_BYTE_VAL			REG8_VAL(GPIO_CTRL_GP63_SD02CD_BYTE_ADDR )
+#define GPIO_OC_GP0_BYTE_VAL 					REG8_VAL(GPIO_OC_GP0_BYTE_ADDR )
+#define GPIO_OC_GP1_BYTE_VAL 					REG8_VAL(GPIO_OC_GP1_BYTE_ADDR )
+#define GPIO_OC_GP2_BYTE_VAL					REG8_VAL(GPIO_OC_GP2_BYTE_ADDR )
+#define GPIO_OC_GP4_VDOUT_7_0_BYTE_VAL			REG8_VAL(GPIO_OC_GP4_VDOUT_7_0_BYTE_ADDR )
+#define GPIO_OC_GP5_VDOUT_15_8_BYTE_VAL			REG8_VAL(GPIO_OC_GP5_VDOUT_15_8_BYTE_ADDR )
+#define GPIO_OC_GP6_VDOUT_23_16_BYTE_VAL		REG8_VAL(GPIO_OC_GP6_VDOUT_23_16_BYTE_ADDR )
+#define GPIO_OC_GP7_VD_BYTE_VAL					REG8_VAL(GPIO_OC_GP7_VD_BYTE_ADDR )
+#define GPIO_OC_GP8_VDIN_BYTE_VAL				REG8_VAL(GPIO_OC_GP8_VDIN_BYTE_ADDR )
+#define GPIO_OC_GP9_VSYNC_BYTE_VAL 				REG8_VAL(GPIO_OC_GP9_VSYNC_BYTE_ADDR )
+#define GPIO_OC_GP10_I2S_BYTE_VAL				REG8_VAL(GPIO_OC_GP10_I2S_BYTE_ADDR )
+#define GPIO_OC_GP11_I2S_BYTE_VAL      			REG8_VAL(GPIO_OC_GP11_I2S_BYTE_ADDR )
+#define GPIO_OC_GP12_SPI_BYTE_VAL				REG8_VAL(GPIO_OC_GP12_SPI_BYTE_ADDR )
+#define GPIO_OC_GP13_SD0_BYTE_VAL   		REG8_VAL(GPIO_OC_GP13_SD0_BYTE_ADDR )
+#define GPIO_OC_GP14_NAND_SD1_BYTE_VAL			REG8_VAL(GPIO_OC_GP14_NAND_SD1_BYTE_ADDR )
+#define GPIO_OC_GP15_NAND_BYTE_VAL				REG8_VAL(GPIO_OC_GP15_NAND_BYTE_ADDR )
+#define GPIO_OC_GP16_NAND_SD1_BYTE_VAL			REG8_VAL(GPIO_OC_GP16_NAND_SD1_BYTE_ADDR )
+#define GPIO_OC_GP17_I2C_BYTE_VAL       		REG8_VAL(GPIO_OC_GP17_I2C_BYTE_ADDR )
+#define GPIO_OC_GP18_UART_BYTE_VAL				REG8_VAL(GPIO_OC_GP18_UART_BYTE_ADDR )
+#define GPIO_OC_GP19_SD2_BYTE_VAL   	    	REG8_VAL(GPIO_OC_GP19_SD2_BYTE_ADDR )
+#define GPIO_OC_GP20_PWM0_BYTE_VAL       		REG8_VAL(GPIO_OC_GP20_PWM0_BYTE_ADDR )
+#define GPIO_OC_GP21_HDMI_BYTE_VAL       		REG8_VAL(GPIO_OC_GP21_HDMI_BYTE_ADDR )
+#define GPIO_OC_GP22_I2C3_BYTE_VAL	     	  	REG8_VAL(GPIO_OC_GP22_I2C3_BYTE_ADDR )
+#define GPIO_OC_GP24_SF_BYTE_VAL				REG8_VAL(GPIO_OC_GP24_SF_BYTE_ADDR )
+#define GPIO_OC_GP26_PCM_BYTE_VAL       		REG8_VAL(GPIO_OC_GP26_PCM_BYTE_ADDR )
+#define GPIO_OC_GP60_USB_BYTE_VAL				REG8_VAL(GPIO_OC_GP60_USB_BYTE_ADDR )
+#define GPIO_OC_GP62_WAKEUP_SUS_BYTE_VAL		REG8_VAL(GPIO_OC_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define GPIO_OC_GP63_SD02CD_BYTE_VAL			REG8_VAL(GPIO_OC_GP63_SD02CD_BYTE_ADDR )
+#define GPIO_OD_GP0_BYTE_VAL 					REG8_VAL(GPIO_OD_GP0_BYTE_ADDR )
+#define GPIO_OD_GP1_BYTE_VAL 					REG8_VAL(GPIO_OD_GP1_BYTE_ADDR )
+#define GPIO_OD_GP2_BYTE_VAL					REG8_VAL(GPIO_OD_GP2_BYTE_ADDR )
+#define GPIO_OD_GP4_VDOUT_7_0_BYTE_VAL			REG8_VAL(GPIO_OD_GP4_VDOUT_7_0_BYTE_ADDR )
+#define GPIO_OD_GP5_VDOUT_15_8_BYTE_VAL			REG8_VAL(GPIO_OD_GP5_VDOUT_15_8_BYTE_ADDR )
+#define GPIO_OD_GP6_VDOUT_23_16_BYTE_VAL		REG8_VAL(GPIO_OD_GP6_VDOUT_23_16_BYTE_ADDR )
+#define GPIO_OD_GP7_VD_BYTE_VAL					REG8_VAL(GPIO_OD_GP7_VD_BYTE_ADDR )
+#define GPIO_OD_GP8_VDIN_BYTE_VAL				REG8_VAL(GPIO_OD_GP8_VDIN_BYTE_ADDR )
+#define GPIO_OD_GP9_VSYNC_BYTE_VAL 				REG8_VAL(GPIO_OD_GP9_VSYNC_BYTE_ADDR )
+#define GPIO_OD_GP10_I2S_BYTE_VAL				REG8_VAL(GPIO_OD_GP10_I2S_BYTE_ADDR )
+#define GPIO_OD_GP11_I2S_BYTE_VAL      			REG8_VAL(GPIO_OD_GP11_I2S_BYTE_ADDR )
+#define GPIO_OD_GP12_SPI_BYTE_VAL				REG8_VAL(GPIO_OD_GP12_SPI_BYTE_ADDR )
+#define GPIO_OD_GP13_SD0_BYTE_VAL   		REG8_VAL(GPIO_OD_GP13_SD0_BYTE_ADDR )
+#define GPIO_OD_GP14_NAND_SD1_BYTE_VAL			REG8_VAL(GPIO_OD_GP14_NAND_SD1_BYTE_ADDR )
+#define GPIO_OD_GP15_NAND_BYTE_VAL				REG8_VAL(GPIO_OD_GP15_NAND_BYTE_ADDR )
+#define GPIO_OD_GP16_NAND_SD1_BYTE_VAL			REG8_VAL(GPIO_OD_GP16_NAND_SD1_BYTE_ADDR )
+#define GPIO_OD_GP17_I2C_BYTE_VAL       		REG8_VAL(GPIO_OD_GP17_I2C_BYTE_ADDR )
+#define GPIO_OD_GP18_UART_BYTE_VAL				REG8_VAL(GPIO_OD_GP18_UART_BYTE_ADDR )
+#define GPIO_OD_GP19_SD2_BYTE_VAL   	    	REG8_VAL(GPIO_OD_GP19_SD2_BYTE_ADDR )
+#define GPIO_OD_GP20_PWM0_BYTE_VAL       		REG8_VAL(GPIO_OD_GP20_PWM0_BYTE_ADDR )
+#define GPIO_OD_GP21_HDMI_BYTE_VAL       		REG8_VAL(GPIO_OD_GP21_HDMI_BYTE_ADDR )
+#define GPIO_OD_GP23_I2C3_BYTE_VAL	       		REG8_VAL(GPIO_OD_GP23_I2C3_BYTE_ADDR )
+#define GPIO_OD_GP24_SF_BYTE_VAL				REG8_VAL(GPIO_OD_GP24_SF_BYTE_ADDR )
+#define GPIO_OD_GP26_PCM_BYTE_VAL       		REG8_VAL(GPIO_OD_GP26_PCM_BYTE_ADDR )
+#define GPIO_OD_GP60_USB_BYTE_VAL				REG8_VAL(GPIO_OD_GP60_USB_BYTE_ADDR )
+#define GPIO_OD_GP62_WAKEUP_SUS_BYTE_VAL		REG8_VAL(GPIO_OD_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define GPIO_OD_GP63_SD02CD_BYTE_VAL			REG8_VAL(GPIO_OD_GP63_SD02CD_BYTE_ADDR )
+#define STRAP_STATUS_VAL					REG32_VAL(STRAP_STATUS_ADDR )
+#define AHB_CTRL_4BYTE_VAL 					REG32_VAL(AHB_CTRL_4BYTE_ADDR )
+#define USB_OP_CTRL_4BYTE_VAL				REG32_VAL(USB_OP_CTRL_4BYTE_ADDR )
+#define BONDING_OPTION_4BYTE_VAL			REG32_VAL(BONDING_OPTION_4BYTE_ADDR )
+#define PIN_SHARING_SEL_4BYTE_VAL 			REG32_VAL(PIN_SHARING_SEL_4BYTE_ADDR )
+#define TPIU_CLK_DATA_4BYTE_VAL 			REG32_VAL(TPIU_CLK_DATA_4BYTE_ADDR )
+#define GPIO0_INT_REQ_TYPE_VAL				REG8_VAL(GPIO0_INT_REQ_TYPE_ADDR )
+#define GPIO1_INT_REQ_TYPE_VAL				REG8_VAL(GPIO1_INT_REQ_TYPE_ADDR )
+#define GPIO2_INT_REQ_TYPE_VAL				REG8_VAL(GPIO2_INT_REQ_TYPE_ADDR )
+#define GPIO3_INT_REQ_TYPE_VAL				REG8_VAL(GPIO3_INT_REQ_TYPE_ADDR )
+#define GPIO4_INT_REQ_TYPE_VAL				REG8_VAL(GPIO4_INT_REQ_TYPE_ADDR )
+#define GPIO5_INT_REQ_TYPE_VAL				REG8_VAL(GPIO5_INT_REQ_TYPE_ADDR )
+#define GPIO6_INT_REQ_TYPE_VAL				REG8_VAL(GPIO6_INT_REQ_TYPE_ADDR )
+#define GPIO7_INT_REQ_TYPE_VAL				REG8_VAL(GPIO7_INT_REQ_TYPE_ADDR )
+#define GPIO8_INT_REQ_TYPE_VAL				REG8_VAL(GPIO8_INT_REQ_TYPE_ADDR )
+#define GPIO9_INT_REQ_TYPE_VAL				REG8_VAL(GPIO9_INT_REQ_TYPE_ADDR )
+#define GPIO10_INT_REQ_TYPE_VAL				REG8_VAL(GPIO10_INT_REQ_TYPE_ADDR )
+#define GPIO11_INT_REQ_TYPE_VAL				REG8_VAL(GPIO11_INT_REQ_TYPE_ADDR )
+#define GPIO12_INT_REQ_TYPE_VAL				REG8_VAL(GPIO12_INT_REQ_TYPE_ADDR )
+#define GPIO13_INT_REQ_TYPE_VAL				REG8_VAL(GPIO13_INT_REQ_TYPE_ADDR )
+#define GPIO18_INT_REQ_TYPE_VAL				REG8_VAL(GPIO18_INT_REQ_TYPE_ADDR )
+#define GPIO19_INT_REQ_TYPE_VAL				REG8_VAL(GPIO19_INT_REQ_TYPE_ADDR )
+#define VOUT20_INT_REQ_TYPE_VAL				REG8_VAL(VOUT20_INT_REQ_TYPE_ADDR )
+#define VOUT21_INT_REQ_TYPE_VAL				REG8_VAL(VOUT21_INT_REQ_TYPE_ADDR )
+#define VOUT22_INT_REQ_TYPE_VAL				REG8_VAL(VOUT22_INT_REQ_TYPE_ADDR )
+#define VOUT23_INT_REQ_TYPE_VAL				REG8_VAL(VOUT23_INT_REQ_TYPE_ADDR )
+#define GPIO20_INT_REQ_TYPE_VAL				REG8_VAL(GPIO20_INT_REQ_TYPE_ADDR )
+#define GPIO21_INT_REQ_TYPE_VAL				REG8_VAL(GPIO21_INT_REQ_TYPE_ADDR )
+#define GPIO22_INT_REQ_TYPE_VAL				REG8_VAL(GPIO22_INT_REQ_TYPE_ADDR )
+#define GPIO23_INT_REQ_TYPE_VAL				REG8_VAL(GPIO23_INT_REQ_TYPE_ADDR )
+#define GPIO24_INT_REQ_TYPE_VAL				REG8_VAL(GPIO24_INT_REQ_TYPE_ADDR )
+#define GPIO25_INT_REQ_TYPE_VAL				REG8_VAL(GPIO25_INT_REQ_TYPE_ADDR )
+#define GPIO0_INT_REQ_STS_VAL				REG8_VAL(GPIO0_INT_REQ_STS_ADDR )
+#define GPIO1_INT_REQ_STS_VAL				REG8_VAL(GPIO1_INT_REQ_STS_ADDR )
+#define GPIO2_INT_REQ_STS_VAL				REG8_VAL(GPIO2_INT_REQ_STS_ADDR )
+#define GPIO3_INT_REQ_STS_VAL				REG8_VAL(GPIO3_INT_REQ_STS_ADDR )
+#define DRV_DVO_CLK_BYTE_VAL				REG8_VAL(DRV_DVO_CLK_BYTE_ADDR )
+#define DRV_DVO_VDEN_BYTE_VAL				REG8_VAL(DRV_DVO_VDEN_BYTE_ADDR )
+#define SD0_DPCTL_4BYTE_VAL					REG32_VAL(SD0_DPCTL_4BYTE_ADDR )
+#define SD0_DNCTL_4BYTE_VAL					REG32_VAL(SD0_DNCTL_4BYTE_ADDR )
+#define DRV_SD0_USB_BYTE_VAL				REG8_VAL(DRV_SD0_USB_BYTE_ADDR )	
+#define DRV_USB_SWOC0_BYTE_VAL				REG8_VAL(DRV_USB_SWOC0_BYTE_ADDR )
+#define DRV_USB_OC12_BYTE_VAL				REG8_VAL(DRV_USB_OC12_BYTE_ADDR )
+#define DRV_USBOC3_CIR_BYTE_VAL				REG8_VAL(DRV_USBOC3_CIR_BYTE_ADDR )
+#define DRV_PWREN_BYTE_VAL					REG8_VAL(DRV_PWREN_BYTE_ADDR )
+#define DRV_PWREN_WAKEUP0_BYTE_VAL			REG8_VAL(DRV_PWREN_WAKEUP0_BYTE_ADDR )
+#define DRV_SUSGP01_BYTE_VAL				REG8_VAL(DRV_SUSGP01_BYTE_ADDR )
+#define DRV_WAKEUP23_BYTE_VAL				REG8_VAL(DRV_WAKEUP23_BYTE_ADDR )
+#define DRV_WAKEUP45_BYTE_VAL				REG8_VAL(DRV_WAKEUP45_BYTE_ADDR )
+#define DRV_I2C_BYTE_VAL					REG8_VAL(DRV_I2C_BYTE_ADDR )
+#define DRV_HDMI_BYTE_VAL					REG8_VAL(DRV_HDMI_BYTE_ADDR )	
+#define PULL_EN_GP0_BYTE_VAL				REG8_VAL(PULL_EN_GP0_BYTE_ADDR )
+#define PULL_EN_GP1_BYTE_VAL				REG8_VAL(PULL_EN_GP1_BYTE_ADDR )
+#define PULL_EN_GP2_BYTE_VAL				REG8_VAL(PULL_EN_GP2_BYTE_ADDR )
+#define PULL_EN_GP4_VDOUT_7_0_BYTE_VAL		REG8_VAL(PULL_EN_GP4_VDOUT_7_0_BYTE_ADDR )
+#define PULL_EN_GP5_VDOUT_15_8_BYTE_VAL		REG8_VAL(PULL_EN_GP5_VDOUT_15_8_BYTE_ADDR )
+#define PULL_EN_GP6_VDOUT_23_16_BYTE_VAL	REG8_VAL(PULL_EN_GP6_VDOUT_23_16_BYTE_ADDR )
+#define PULL_EN_GP7_VD_BYTE_VAL     		REG8_VAL(PULL_EN_GP7_VD_BYTE_ADDR )
+#define PULL_EN_GP8_VDIN_BYTE_VAL   		REG8_VAL(PULL_EN_GP8_VDIN_BYTE_ADDR )
+#define PULL_EN_GP9_VSYNC_BYTE_VAL 			REG8_VAL(PULL_EN_GP9_VSYNC_BYTE_ADDR )
+#define PULL_EN_GP10_I2S_BYTE_VAL 			REG8_VAL(PULL_EN_GP10_I2S_BYTE_ADDR )
+#define PULL_EN_GP11_I2S_BYTE_VAL     		REG8_VAL(PULL_EN_GP11_I2S_BYTE_ADDR )
+#define PULL_EN_GP12_SPI_BYTE_VAL			REG8_VAL(PULL_EN_GP12_SPI_BYTE_ADDR )
+#define PULL_EN_GP13_SD0_BYTE_VAL       	REG8_VAL(PULL_EN_GP13_SD0_BYTE_ADDR )
+#define PULL_EN_GP14_NAND_BYTE_VAL      	REG8_VAL(PULL_EN_GP14_NAND_BYTE_ADDR )
+#define PULL_EN_GP15_NAND_BYTE_VAL			REG8_VAL(PULL_EN_GP15_NAND_BYTE_ADDR )
+#define PULL_EN_GP16_NANDIO_BYTE_VAL		REG8_VAL(PULL_EN_GP16_NANDIO_BYTE_ADDR )
+#define PULL_EN_GP17_I2C_BYTE_VAL			REG8_VAL(PULL_EN_GP17_I2C_BYTE_ADDR )
+#define PULL_EN_GP18_UART_BYTE_VAL			REG8_VAL(PULL_EN_GP18_UART_BYTE_ADDR )
+#define PULL_EN_GP19_SD2_BYTE_VAL			REG8_VAL(PULL_EN_GP19_SD2_BYTE_ADDR )
+#define PULL_EN_GP20_PWM0_BYTE_VAL			REG8_VAL(PULL_EN_GP20_PWM0_BYTE_ADDR )
+#define PULL_EN_GP21_HDMI_BYTE_VAL      	REG8_VAL(PULL_EN_GP21_HDMI_BYTE_ADDR )
+#define PULL_EN_GP23_I2C3_BYTE_VAL			REG8_VAL(PULL_EN_GP23_I2C3_BYTE_ADDR )
+#define PULL_EN_GP24_SF_BYTE_VAL			REG8_VAL(PULL_EN_GP24_SF_BYTE_ADDR )
+#define PULL_EN_GP26_PCM_BYTE_VAL			REG8_VAL(PULL_EN_GP26_PCM_BYTE_ADDR )
+#define PULL_EN_GP60_USB_BYTE_VAL			REG8_VAL(PULL_EN_GP60_USB_BYTE_ADDR )
+#define PULL_EN_GP62_WAKEUP_SUS_BYTE_VAL	REG8_VAL(PULL_EN_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define PULL_EN_GP63_SD02_BYTE_VAL			REG8_VAL(PULL_EN_GP63_SD02_BYTE_ADDR )
+#define PULL_CTRL_GP0_BYTE_VAL				REG8_VAL(PULL_CTRL_GP0_BYTE_ADDR )
+#define PULL_CTRL_GP1_BYTE_VAL				REG8_VAL(PULL_CTRL_GP1_BYTE_ADDR )
+#define PULL_CTRL_GP2_BYTE_VAL				REG8_VAL(PULL_CTRL_GP2_BYTE_ADDR )
+#define PULL_CTRL_GP4_VDOUT_7_0_BYTE_VAL	REG8_VAL(PULL_CTRL_GP4_VDOUT_7_0_BYTE_ADDR )
+#define PULL_CTRL_GP5_VDOUT_15_8_BYTE_VAL	REG8_VAL(PULL_CTRL_GP5_VDOUT_15_8_BYTE_ADDR )
+#define PULL_CTRL_GP6_VDOUT_23_16_BYTE_VAL	REG8_VAL(PULL_CTRL_GP6_VDOUT_23_16_BYTE_ADDR )
+#define PULL_CTRL_GP7_VD_BYTE_VAL			REG8_VAL(PULL_CTRL_GP7_VD_BYTE_ADDR )
+#define PULL_CTRL_GP8_VDIN_BYTE_VAL			REG8_VAL(PULL_CTRL_GP8_VDIN_BYTE_ADDR )
+#define PULL_CTRL_GP9_VSYNC_BYTE_VAL		REG8_VAL(PULL_CTRL_GP9_VSYNC_BYTE_ADDR )
+#define PULL_CTRL_GP10_I2S_BYTE_VAL			REG8_VAL(PULL_CTRL_GP10_I2S_BYTE_ADDR )
+#define PULL_CTRL_GP11_I2S_BYTE_VAL			REG8_VAL(PULL_CTRL_GP11_I2S_BYTE_ADDR )
+#define PULL_CTRL_GP12_SPI_BYTE_VAL			REG8_VAL(PULL_CTRL_GP12_SPI_BYTE_ADDR )
+#define PULL_CTRL_GP13_SD0_BYTE_VAL			REG8_VAL(PULL_CTRL_GP13_SD0_BYTE_ADDR )
+#define PULL_CTRL_GP14_NAND_BYTE_VAL       	REG8_VAL(PULL_CTRL_GP14_NAND_BYTE_ADDR )
+#define PULL_CTRL_GP15_NAND_BYTE_VAL		REG8_VAL(PULL_CTRL_GP15_NAND_BYTE_ADDR )
+#define PULL_CTRL_GP16_NANDIO_BYTE_VAL		REG8_VAL(PULL_CTRL_GP16_NANDIO_BYTE_ADDR )
+#define PULL_CTRL_GP17_I2C_BYTE_VAL     	REG8_VAL(PULL_CTRL_GP17_I2C_BYTE_ADDR )
+#define PULL_CTRL_GP18_UART_BYTE_VAL     	REG8_VAL(PULL_CTRL_GP18_UART_BYTE_ADDR )
+#define PULL_CTRL_GP19_SD2_BYTE_VAL     	REG8_VAL(PULL_CTRL_GP19_SD2_BYTE_ADDR )
+#define PULL_CTRL_GP20_PWM0_BYTE_VAL      	REG8_VAL(PULL_CTRL_GP20_PWM0_BYTE_ADDR )
+#define PULL_CTRL_GP21_HDMI_BYTE_VAL		REG8_VAL(PULL_CTRL_GP21_HDMI_BYTE_ADDR )
+#define PULL_CTRL_GP23_I2C3_BYTE_VAL		REG8_VAL(PULL_CTRL_GP23_I2C3_BYTE_ADDR )
+#define PULL_CTRL_GP24_SF_BYTE_VAL     		REG8_VAL(PULL_CTRL_GP24_SF_BYTE_ADDR )
+#define PULL_CTRL_GP26_PCM_BYTE_VAL			REG8_VAL(PULL_CTRL_GP26_PCM_BYTE_ADDR )
+#define PULL_CTRL_GP27_SD0_BYTE_VAL			REG8_VAL(PULL_CTRL_GP27_SD0_BYTE_ADDR )
+#define PULL_CTRL_GP60_USB_BYTE_VAL			REG8_VAL(PULL_CTRL_GP60_USB_BYTE_ADDR )
+#define PULL_CTRL_GP62_WAKEUP_SUS_BYTE_VAL	REG8_VAL(PULL_CTRL_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define PULL_CTRL_GP63_SD02_BYTE_VAL		REG8_VAL(PULL_CTRL_GP63_SD02_BYTE_ADDR )
+#define DRV_GPIO_7_0_4BYTE_VAL				REG32_VAL(DRV_GPIO_7_0_4BYTE_ADDR )
+#define DRV_GPIO_13_8_4BYTE_VAL				REG32_VAL(DRV_GPIO_13_8_4BYTE_ADDR )
+#define DRV_GPIO_19_14_4BYTE_VAL			REG32_VAL(DRV_GPIO_19_14_4BYTE_ADDR )
+#define DRV_VDIN_3_0_4BYTE_VAL				REG32_VAL(DRV_VDIN_3_0_4BYTE_ADDR )
+#define DRV_VDIN_4_6_4BYTE_VAL				REG32_VAL(DRV_VDIN_3_0_4BYTE_ADDR )
+#define DRV_VDIN_SPI_4BYTE_VAL				REG32_VAL(DRV_VDIN_SPI_4BYTE_ADDR )
+#define DRV_SPI_NAND_4BYTE_VAL				REG32_VAL(DRV_SPI_NAND_4BYTE_ADDR )
+#define DRV_NAND_4BYTE_VAL					REG32_VAL(DRV_NAND_4BYTE_ADDR )
+#define DRV_NANDIO_4BYTE_VAL				REG32_VAL(DRV_NANDIO_4BYTE_ADDR )
+#define DRV_HDMI_I2C_4BYTE_VAL				REG32_VAL(DRV_HDMI_I2C_4BYTE_ADDR )
+#define DRV_I2C_SD0_4BYTE_VAL				REG32_VAL(DRV_I2C_SD0_4BYTE_ADDR )
+#define DRV_SD0_SD2_4BYTE_VAL				REG32_VAL(DRV_SD0_SD2_4BYTE_ADDR )
+#define DRV_SD2_I2S_4BYTE_VAL				REG32_VAL(DRV_SD2_I2S_4BYTE_ADDR )
+#define DRV_I2S_UART_4BYTE_VAL				REG32_VAL(DRV_I2S_UART_4BYTE_ADDR )
+#define DRV_UART_4BYTE_VAL					REG32_VAL(DRV_UART_4BYTE_ADDR )
+#define DRV_SF_JTAGT_4BYTE_VAL				REG32_VAL(DRV_SF_JTAGT_4BYTE_ADDR )
+#define DRV_JTAGT_PWM_4BYTE_VAL				REG32_VAL(DRV_JTAGT_PWM_4BYTE_ADDR )
+#define DRV_PCM_BYTE_VAL					REG8_VAL(DRV_PCM_BYTE_ADDR )
+#define DRV_SPI_BYTE_VAL					REG8_VAL(DRV_SPI_BYTE_ADDR )
+
+#define GPIO_STRAP_STS_VAL  		REG32_VAL(0x0100+BA_GPIO)
+
+/* [Rx300] GPIO Interrupt Request Type Register */
+#define GPIO_IRQT_LOW	  	0
+#define GPIO_IRQT_HIGH		BIT0
+#define GPIO_IRQT_FALLING	BIT1
+#define GPIO_IRQT_RISING	(BIT1 | BIT0)
+#define GPIO_IRQT_DOUBLE	BIT2
+
+/* GPIO Control Register for I2C */
+#define GPIO_I2C0_SCL	BIT0
+#define GPIO_I2C0_SDA	BIT1
+#define GPIO_I2C1_SCL	BIT2
+#define GPIO_I2C1_SDA	BIT3
+#define GPIO_I2C2_SCL	BIT4
+#define GPIO_I2C2_SDA	BIT5
+#define GPIO_I2C3_SCL	BIT0
+#define GPIO_I2C3_SDA	BIT1
+#define GPIO_I2C0_SCL_PULL_EN BIT0
+#define GPIO_I2C0_SDA_PULL_EN BIT1
+#define GPIO_I2C1_SCL_PULL_EN BIT2
+#define GPIO_I2C1_SDA_PULL_EN BIT3
+#define GPIO_I2C2_SCL_PULL_EN BIT4
+#define GPIO_I2C2_SDA_PULL_EN BIT5
+#define GPIO_I2C3_SCL_PULL_EN BIT0
+#define GPIO_I2C3_SDA_PULL_EN BIT1
+
+#endif
+/*=== END wmt_gpio.h ==========================================================*/
+