init commit via android 4.4 uboot

6 files changed, 1029 insertions, 0 deletions

diff --git a/board/rsdproto/Makefile b/board/rsdproto/Makefile
new file mode 100755
index 0000000..9934787
--- /dev/null
+++ b/board/rsdproto/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= rsdproto.o flash.o
+SOBJS	:= flash_asm.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/rsdproto/config.mk b/board/rsdproto/config.mk
new file mode 100755
index 0000000..5844ec1
--- /dev/null
+++ b/board/rsdproto/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MBX8xx boards
+#
+
+TEXT_BASE = 0xff000000
+/*TEXT_BASE  = 0x00200000 */
diff --git a/board/rsdproto/flash.c b/board/rsdproto/flash.c
new file mode 100755
index 0000000..5ad3218
--- /dev/null
+++ b/board/rsdproto/flash.c
@@ -0,0 +1,402 @@
+/*
+ * (C) Copyright 2000
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for AM290[48]0B devices
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* flash hardware ids */
+#define VENDOR_AMD     0x0001
+#define AMD_29DL323C_B 0x2253
+
+/* Define this to include autoselect sequence in flash_init(). Does NOT
+ * work when executing from flash itself, so this should be turned
+ * on only when debugging the RAM version.
+ */
+#undef WITH_AUTOSELECT
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if 1
+#define D(x)
+#else
+#define D(x) printf x
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static unsigned char write_ull(flash_info_t *info,
+			       unsigned long address,
+			       volatile unsigned long long data);
+
+/* from flash_asm.S */
+extern void ull_write(unsigned long long volatile *address,
+		      unsigned long long volatile *data);
+extern void ull_read(unsigned long long volatile *address,
+		     unsigned long long volatile *data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+    int i;
+    ulong addr;
+
+#ifdef WITH_AUTOSELECT
+	{
+		unsigned long long *f_addr = (unsigned long long *)PHYS_FLASH;
+		unsigned long long f_command, vendor, device;
+		/* Perform Autoselect */
+		f_command 	= 0x00AA00AA00AA00AAULL;
+		ull_write(&f_addr[0x555], &f_command);
+		f_command 	= 0x0055005500550055ULL;
+		ull_write(&f_addr[0x2AA], &f_command);
+		f_command 	= 0x0090009000900090ULL;
+		ull_write(&f_addr[0x555], &f_command);
+		ull_read(&f_addr[0], &vendor);
+		vendor &= 0xffff;
+		ull_read(&f_addr[1], &device);
+		device &= 0xffff;
+		f_command 	= 0x00F000F000F000F0ULL;
+		ull_write(&f_addr[0x555], &f_command);
+		if (vendor != VENDOR_AMD || device != AMD_29DL323C_B)
+		  return 0;
+	}
+#endif
+
+    /* Init: no FLASHes known */
+    for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+    }
+
+	/* 1st bank: 8 x 32 KB sectors */
+	flash_info[0].flash_id = VENDOR_AMD << 16 | AMD_29DL323C_B;
+	flash_info[0].sector_count = 8;
+	flash_info[0].size = flash_info[0].sector_count * 32 * 1024;
+	addr = PHYS_FLASH;
+    for(i = 0; i < flash_info[0].sector_count; i++) {
+		flash_info[0].start[i] = addr;
+		addr += flash_info[0].size / flash_info[0].sector_count;
+	}
+	/* 1st bank: 63 x 256 KB sectors */
+	flash_info[1].flash_id = VENDOR_AMD << 16 | AMD_29DL323C_B;
+	flash_info[1].sector_count = 63;
+	flash_info[1].size = flash_info[1].sector_count * 256 * 1024;
+    for(i = 0; i < flash_info[1].sector_count; i++) {
+		flash_info[1].start[i] = addr;
+		addr += flash_info[1].size / flash_info[1].sector_count;
+	}
+
+	/*
+	 * protect monitor and environment sectors
+	 */
+
+#if CFG_MONITOR_BASE >= PHYS_FLASH
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[1]);
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		      &flash_info[0]);
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		      &flash_info[1]);
+#endif
+
+    return flash_info[0].size + flash_info[1].size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+    }
+
+    switch (info->flash_id >> 16) {
+    case VENDOR_AMD:
+		printf ("AMD ");
+		break;
+    default:
+		printf ("Unknown Vendor ");
+		break;
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+    case AMD_29DL323C_B:
+		printf ("AM29DL323CB (32 Mbit)\n");
+		break;
+    default:
+		printf ("Unknown Chip Type\n");
+		break;
+    }
+
+    printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+    printf ("  Sector Start Addresses:");
+    for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+		  printf ("\n   ");
+		printf (" %08lX%s",
+				info->start[i],
+				info->protect[i] ? " (RO)" : "     "
+				);
+    }
+    printf ("\n");
+    return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    int flag, prot, sect, l_sect;
+    ulong start;
+	unsigned long long volatile *f_addr;
+	unsigned long long volatile f_command;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+    }
+
+    prot = 0;
+    for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+    }
+    if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+    } else {
+		printf ("\n");
+    }
+
+	f_addr 	= (unsigned long long *)info->start[0];
+	f_command 	= 0x00AA00AA00AA00AAULL;
+	ull_write(&f_addr[0x555], &f_command);
+	f_command 	= 0x0055005500550055ULL;
+	ull_write(&f_addr[0x2AA], &f_command);
+	f_command 	= 0x0080008000800080ULL;
+	ull_write(&f_addr[0x555], &f_command);
+	f_command 	= 0x00AA00AA00AA00AAULL;
+	ull_write(&f_addr[0x555], &f_command);
+	f_command 	= 0x0055005500550055ULL;
+	ull_write(&f_addr[0x2AA], &f_command);
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    /* Start erase on unprotected sectors */
+    for (l_sect = -1, sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+
+			f_addr 	=
+			  (unsigned long long *)(info->start[sect]);
+			f_command 	= 0x0030003000300030ULL;
+			ull_write(f_addr, &f_command);
+			l_sect = sect;
+		}
+    }
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+      enable_interrupts();
+
+	start = get_timer (0);
+	do
+	{
+		if (get_timer(start) > CFG_FLASH_ERASE_TOUT)
+		{	/* write reset command, command address is unimportant */
+			/* this command turns the flash back to read mode     */
+			f_addr =
+			  (unsigned long long *)(info->start[l_sect]);
+			f_command 	= 0x00F000F000F000F0ULL;
+			ull_write(f_addr, &f_command);
+			printf (" timeout\n");
+			return 1;
+	}
+	} while(*f_addr != 0xFFFFFFFFFFFFFFFFULL);
+
+    printf (" done\n");
+    return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    unsigned long cp, wp;
+	unsigned long long data;
+    int i, l, rc;
+
+    wp = (addr & ~7);	/* get lower long long aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<8 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<8; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_ull(info, wp, data)) != 0) {
+			return rc;
+		}
+		wp += 4;
+    }
+
+    /*
+     * handle long long aligned part
+     */
+    while (cnt >= 8) {
+		data = 0;
+		for (i=0; i<8; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_ull(info, wp, data)) != 0) {
+			return rc;
+		}
+		wp  += 8;
+		cnt -= 8;
+    }
+
+    if (cnt == 0) {
+		return ERR_OK;
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i=0, cp=wp; i<8 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+    }
+    for (; i<8; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+    }
+
+    return write_ull(info, wp, data);
+}
+
+/*---------------------------------------------------------------------------
+*
+* FUNCTION NAME:  write_ull
+*
+* DESCRIPTION:   writes 8 bytes to flash
+*
+* EXTERNAL EFFECT: nothing
+*
+* PARAMETERS:   32 bit long pointer to address, 64 bit long pointer to data
+*
+* RETURNS: 	0 if OK, 1 if timeout, 4 if parameter error
+*--------------------------------------------------------------------------*/
+
+static unsigned char write_ull(flash_info_t *info,
+							   unsigned long address,
+							   volatile unsigned long long data)
+{
+	static unsigned long long f_command;
+	static unsigned long long *f_addr;
+	ulong start;
+
+	/* address muss be 8-aligned! */
+	if (address & 0x7)
+	  return ERR_ALIGN;
+
+	f_addr 	= (unsigned long long *)info->start[0];
+	f_command 	= 0x00AA00AA00AA00AAULL;
+	ull_write(&f_addr[0x555], &f_command);
+	f_command 	= 0x0055005500550055ULL;
+	ull_write(&f_addr[0x2AA], &f_command);
+	f_command 	= 0x00A000A000A000A0ULL;
+	ull_write(&f_addr[0x555], &f_command);
+
+	f_addr 	= (unsigned long long *)address;
+	f_command 	= data;
+	ull_write(f_addr, &f_command);
+
+	start = get_timer (0);
+	do
+	{
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+		{
+			/* write reset command, command address is unimportant */
+			/* this command turns the flash back to read mode     */
+			f_addr 	= (unsigned long long *)info->start[0];
+			f_command 	= 0x00F000F000F000F0ULL;
+			ull_write(f_addr, &f_command);
+			return ERR_TIMOUT;
+		}
+	} while(*((unsigned long long *)address) != data);
+
+	return 0;
+}
diff --git a/board/rsdproto/flash_asm.S b/board/rsdproto/flash_asm.S
new file mode 100755
index 0000000..557cac0
--- /dev/null
+++ b/board/rsdproto/flash_asm.S
@@ -0,0 +1,39 @@
+/*
+ * -*- mode:c -*-
+ *
+ * (C) Copyright 2000
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ *
+ * void ull_write(unsigned long long volatile *address,
+ *                unsigned long long volatile *data)
+ * r3 = address
+ * r4 = data
+ *
+ * void ull_read(unsigned long long volatile *address,
+ *                unsigned long long volatile *data)
+ * r3 = address
+ * r4 = data
+ *
+ * Uses the floating point unit to read and write 64 bit wide
+ * data (unsigned long long) on the 60x bus. This is necessary
+ * because all 4 flash chips use the /WE line from byte lane 0
+ *
+ * IMPORTANT: data should always be 8-aligned, otherwise an exception will
+ * occur.
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+	.globl	ull_write
+ull_write:
+	lfd		0,0(r4)
+	stfd	0,0(r3)
+	blr
+
+	.globl	ull_read
+ull_read:
+	lfd		0, 0(r3)
+	stfd	0, 0(r4)
+	blr
diff --git a/board/rsdproto/rsdproto.c b/board/rsdproto/rsdproto.c
new file mode 100755
index 0000000..bf4fd53
--- /dev/null
+++ b/board/rsdproto/rsdproto.c
@@ -0,0 +1,378 @@
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <i2c.h>
+
+/* define to initialise the SDRAM on the local bus */
+#undef INIT_LOCAL_BUS_SDRAM
+
+/* I2C Bus adresses for PPC & Protocol board */
+#define PPC8260_I2C_ADR		0x30	/*(0)011.0000 */
+#define LM84_PPC_I2C_ADR	0x2A	/*(0)010.1010 */
+#define LM84_SHARC_I2C_ADR	0x29	/*(0)010.1001 */
+#define VIRTEX_I2C_ADR		0x25	/*(0)010.0101 */
+#define X24645_PPC_I2C_ADR	0x00	/*(0)00X.XXXX  -> be careful ! No other i2c-chip should have an adress beginning with (0)00 !!! */
+#define RS5C372_PPC_I2C_ADR	0x32	/*(0)011.0010  -> this adress is programmed by the manufacturer and cannot be changed !!! */
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA30 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA29 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA28 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA27 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA26 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA25 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA24 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA23 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA22 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA21 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA20 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA19 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA18 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA17 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA16 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA15 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA14 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA13 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA12 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA11 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA10 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA9  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA8  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA7  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA6  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA5  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA4  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA3  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA2  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA1  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA0  */ {   0,   0,   0,   0,   0,   0   }
+    },
+
+
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB16 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB15 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB14 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB13 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB12 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB11 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB10 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB9  */ {   0,   0,   0,   0,   0,   0   },
+	/* PB8  */ {   0,   0,   0,   0,   0,   0   },
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   },
+	/* PB6  */ {   0,   0,   0,   0,   0,   0   },
+	/* PB5  */ {   0,   0,   0,   0,   0,   0   },
+	/* PB4  */ {   0,   0,   0,   0,   0,   0   },
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC30 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC29 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC28 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC27 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC26 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC25 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC24 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC23 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC22 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC21 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC20 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   },
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* ETHRXCLK: CLK14 */
+	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* ETHTXCLK: CLK15 */
+	/* PC16 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC15 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC14 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 UART CD/ */
+	/* PC13 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC12 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC11 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* ETHMDC: GP */
+	/* PC9  */ {   1,   0,   0,   1,   0,   0   }, /* ETHMDIO: GP */
+	/* PC8  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC7  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC6  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC5  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC4  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC3  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC2  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC1  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC0  */ {   0,   0,   0,   0,   0,   0   }
+    },
+
+
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 UART RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 UART TxD */
+	/* PD29 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD28 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD27 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD26 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD25 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD24 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD23 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD22 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD21 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD20 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD19 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD18 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD17 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD16 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD9  */ {   0,   0,   0,   0,   0,   0   },
+	/* PD8  */ {   0,   0,   0,   0,   0,   0   },
+	/* PD7  */ {   0,   0,   0,   0,   0,   0   },
+	/* PD6  */ {   0,   0,   0,   0,   0,   0   },
+	/* PD5  */ {   0,   0,   0,   0,   0,   0   },
+	/* PD4  */ {   0,   0,   0,   0,   0,   0   },
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+struct tm {
+	unsigned int tm_sec;
+	unsigned int tm_min;
+	unsigned int tm_hour;
+	unsigned int tm_wday;
+	unsigned int tm_mday;
+	unsigned int tm_mon;
+	unsigned int tm_year;
+};
+
+void read_RS5C372_time (struct tm *timedate)
+{
+	unsigned char buffer[8];
+
+#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
+
+	if (i2c_read (RS5C372_PPC_I2C_ADR, 0, 1, buffer, sizeof (buffer))) {
+		timedate->tm_sec = BCD_TO_BIN (buffer[0]);
+		timedate->tm_min = BCD_TO_BIN (buffer[1]);
+		timedate->tm_hour = BCD_TO_BIN (buffer[2]);
+		timedate->tm_wday = BCD_TO_BIN (buffer[3]);
+		timedate->tm_mday = BCD_TO_BIN (buffer[4]);
+		timedate->tm_mon = BCD_TO_BIN (buffer[5]);
+		timedate->tm_year = BCD_TO_BIN (buffer[6]) + 2000;
+	} else {
+		/*printf("i2c error %02x\n", rc); */
+		memset (timedate, 0, sizeof (struct tm));
+	}
+}
+
+/* ------------------------------------------------------------------------- */
+
+int read_LM84_temp (int address)
+{
+	unsigned char buffer[8];
+	/*int rc;*/
+
+	if (i2c_read (address, 0, 1, buffer, 1)) {
+		return (int) buffer[0];
+	} else {
+		/*printf("i2c error %02x\n", rc); */
+		return -42;
+	}
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	struct tm timedate;
+	unsigned int ppctemp, prottemp;
+
+	puts ("Board: Rohde & Schwarz 8260 Protocol Board\n");
+
+	/* initialise i2c */
+	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+	read_RS5C372_time (&timedate);
+	printf ("  Time:  %02d:%02d:%02d\n",
+			timedate.tm_hour, timedate.tm_min, timedate.tm_sec);
+	printf ("  Date:  %02d-%02d-%04d\n",
+			timedate.tm_mday, timedate.tm_mon, timedate.tm_year);
+	ppctemp = read_LM84_temp (LM84_PPC_I2C_ADR);
+	prottemp = read_LM84_temp (LM84_SHARC_I2C_ADR);
+	printf ("  Temp:  PPC %d C, Protocol Board %d C\n",
+			ppctemp, prottemp);
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations while still
+ * running in flash
+ */
+
+int misc_init_f (void)
+{
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifdef INIT_LOCAL_BUS_SDRAM
+	volatile uchar *ramaddr8;
+#endif
+	volatile ulong *ramaddr32;
+	ulong sdmr;
+	int i;
+
+	/*
+	 * Only initialize SDRAM when running from FLASH.
+	 * When running from RAM, don't touch it.
+	 */
+	if ((ulong) initdram & 0xff000000) {
+		immap->im_siu_conf.sc_ppc_acr = 0x02;
+		immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
+		immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
+		immap->im_siu_conf.sc_lcl_acr = 0x02;
+		immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
+		immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
+		/*
+		 * Program local/60x bus Transfer Error Status and Control Regs:
+		 * Disable parity errors
+		 */
+		immap->im_siu_conf.sc_tescr1 = 0x00040000;
+		immap->im_siu_conf.sc_ltescr1 = 0x00040000;
+
+		/*
+		 * Perform Power-Up Initialisation of SDRAM (see 8260 UM, 10.4.2)
+		 *
+		 * The appropriate BRx/ORx registers have already
+		 * been set when we get here (see cpu_init_f). The
+		 * SDRAM can be accessed at the address CFG_SDRAM_BASE.
+		 */
+		memctl->memc_mptpr = 0x2000;
+		memctl->memc_mar = 0x0200;
+#ifdef INIT_LOCAL_BUS_SDRAM
+		/* initialise local bus ram
+		 *
+		 * (using the PSRMR_ definitions is NOT an error here
+		 * - the LSDMR has the same fields as the PSDMR!)
+		 */
+		memctl->memc_lsrt = 0x0b;
+		memctl->memc_lurt = 0x00;
+		ramaddr = (uchar *) PHYS_SDRAM_LOCAL;
+		sdmr = CFG_LSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
+		memctl->memc_lsdmr = sdmr | PSDMR_OP_PREA;
+		*ramaddr = 0xff;
+		for (i = 0; i < 8; i++) {
+			memctl->memc_lsdmr = sdmr | PSDMR_OP_CBRR;
+			*ramaddr = 0xff;
+		}
+		memctl->memc_lsdmr = sdmr | PSDMR_OP_MRW;
+		*ramaddr = 0xff;
+		memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_NORM;
+#endif
+		/* initialise 60x bus ram */
+		memctl->memc_psrt = 0x0b;
+		memctl->memc_purt = 0x08;
+		ramaddr32 = (ulong *) PHYS_SDRAM_60X;
+		sdmr = CFG_PSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
+		memctl->memc_psdmr = sdmr | PSDMR_OP_PREA;
+		ramaddr32[0] = 0x00ff00ff;
+		ramaddr32[1] = 0x00ff00ff;
+		memctl->memc_psdmr = sdmr | PSDMR_OP_CBRR;
+		for (i = 0; i < 8; i++) {
+			ramaddr32[0] = 0x00ff00ff;
+			ramaddr32[1] = 0x00ff00ff;
+		}
+		memctl->memc_psdmr = sdmr | PSDMR_OP_MRW;
+		ramaddr32[0] = 0x00ff00ff;
+		ramaddr32[1] = 0x00ff00ff;
+		memctl->memc_psdmr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	}
+
+	/* return the size of the 60x bus ram */
+	return PHYS_SDRAM_60X_SIZE;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations after monitor
+ * has been relocated into ram
+ */
+
+int misc_init_r (void)
+{
+	printf ("misc_init_r\n");
+	return (0);
+}
diff --git a/board/rsdproto/u-boot.lds b/board/rsdproto/u-boot.lds
new file mode 100755
index 0000000..70fc3a5
--- /dev/null
+++ b/board/rsdproto/u-boot.lds
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    /*. = env_offset; */
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}