init commit via android 4.4 uboot

12 files changed, 3957 insertions, 0 deletions

diff --git a/board/eltec/bab7xx/Makefile b/board/eltec/bab7xx/Makefile
new file mode 100755
index 0000000..7d8ed26
--- /dev/null
+++ b/board/eltec/bab7xx/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o pci.o misc.o el_srom.o dc_srom.o l2cache.o
+
+SOBJS	= asm_init.o
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/eltec/bab7xx/asm_init.S b/board/eltec/bab7xx/asm_init.S
new file mode 100755
index 0000000..2a9b33e
--- /dev/null
+++ b/board/eltec/bab7xx/asm_init.S
@@ -0,0 +1,1476 @@
+/*
+ * (C) Copyright 2001 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * ELTEC BAB PPC RAM initialization
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/processor.h>
+#include <74xx_7xx.h>
+#include <mpc106.h>
+#include <version.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+/*
+ * This following contains the entry code for the initialization code
+ * for the MPC 106, a PCI Bridge/Memory Controller.
+ * Register usage:
+ * r0  = ramtest scratch register, toggleError loop counter
+ * r1  = 0xfec0 0cf8 CONFIG_ADDRESS
+ * r2  = 0xfee0 0cfc CONFIG_DATA
+ * r3  = scratch register, subroutine argument and return value, ramtest size
+ * r4  = scratch register, spdRead clock mask, OutHex loop count
+ * r5  = ramtest scratch register
+ * r6  = toggleError 1st value, spdRead port mask
+ * r7  = toggleError 2nd value, ramtest scratch register,
+ *       spdRead scratch register (0x00)
+ * r8  = ramtest scratch register, spdRead scratch register (0x80)
+ * r9  = ramtest scratch register, toggleError loop end, OutHex digit
+ * r10 = ramtest scratch register, spdWriteByte parameter,
+ *        spdReadByte return value, printf pointer to COM1
+ * r11 = startType
+ * r12 = ramtest scratch register, spdRead data mask
+ * r13 = pointer to message block
+ * r14 = pointer to GOT
+ * r15 = scratch register, SPD save
+ * r16 = bank0 size, total memory size
+ * r17 = bank1 size
+ * r18 = bank2 size
+ * r19 = bank3 size
+ * r20 = MCCR1, MSAR1
+ * r21 = MCCR3, MEAR1
+ * r22 = MCCR4, MBER
+ * r23 = EMSAR1
+ * r24 = EMEAR1
+ * r25 = save link register 1st level
+ * r26 = save link register 2nd level
+ * r27 = save link register 3rd level
+ * r30 = pointer to GPIO for spdRead
+ */
+
+
+.globl board_asm_init
+board_asm_init:
+/*
+ * setup pointer to message block
+ */
+    mflr    r25             /* save away link register */
+    bl      get_lnk_reg     /* r3=addr of next instruction */
+    subi    r4, r3, 8       /* r4=board_asm_init addr */
+    addi    r13, r4, (MessageBlock-board_asm_init)
+/*
+ * dcache_disable
+ */
+    mfspr   r3, HID0
+    li      r4, HID0_DCE
+    andc    r3, r3, r4
+    mr      r2, r3
+    ori     r3, r3, HID0_DCI
+    sync
+    mtspr   HID0, r3
+    mtspr   HID0, r2
+    isync
+    sync
+/*
+ * icache_disable
+ */
+    mfspr   r3, HID0
+    li      r4, 0
+    ori     r4, r4, HID0_ICE
+    andc    r3, r3, r4
+    sync
+    mtspr   HID0, r3
+/*
+ * invalidate caches
+ */
+    ori     r3, r3, (HID0_ICE | HID0_ICFI | HID0_DCI | HID0_DCE)
+    or      r4, r4, r3
+    isync
+    mtspr   HID0, r4
+    andc    r4, r4, r3
+    isync
+    mtspr   HID0, r4
+    isync
+/*
+ * icache_enable
+ */
+    mfspr   r3, HID0
+    ori     r3, r3, (HID0_ICE | HID0_ICFI)
+    sync
+    mtspr   HID0, r3
+
+    lis     r1, 0xfec0
+    ori     r1, r1, 0x0cf8
+    lis     r2, 0xfee0
+    ori     r2, r2, 0xcfc
+
+#ifdef CFG_ADDRESS_MAP_A
+/*
+ * Switch to address map A if necessary.
+ */
+    lis     r3, MPC106_REG@h
+    ori     r3, r3, PCI_PICR1
+    stwbrx  r3, 0, r1
+    sync
+    lwbrx   r4, 0, r2
+    sync
+    lis     r0, PICR1_XIO_MODE@h
+    ori     r0, r0, PICR1_XIO_MODE@l
+    andc    r4, r4, r0
+    lis     r0, PICR1_ADDRESS_MAP@h
+    ori     r0, r0, PICR1_ADDRESS_MAP@l
+    or      r4, r4, r0
+    stwbrx  r4, 0, r2
+    sync
+#endif
+
+/*
+ * Do the init for the SIO.
+ */
+    bl      .sioInit
+
+    addi    r3, r13, (MinitLogo-MessageBlock)
+    bl      Printf
+
+    addi    r3, r13, (Mspd01-MessageBlock)
+    bl      Printf
+/*
+ * Memory cofiguration using SPD information stored on the SODIMMs
+ */
+    li      r17, 0
+    li      r18, 0
+    li      r19, 0
+
+    li      r3, 0x0002          /* get RAM type from spd for bank0/1 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, -1        /* error ? */
+    bne     noSpdError
+
+    addi    r3, r13, (Mfail-MessageBlock)
+    bl      Printf
+
+    li      r6, 0xe0            /* error codes in r6 and r7  */
+    li      r7, 0x00
+    b       toggleError         /* fail - loop forever */
+
+noSpdError:
+    mr      r15, r3             /* save r3 */
+
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+
+    cmpli   0, 0, r15, 0x0001   /* FPM ? */
+    beq     configFPM
+    cmpli   0, 0, r15, 0x0002   /* EDO ? */
+    beq     configEDO
+    cmpli   0, 0, r15, 0x0004   /* SDRAM ? */
+    beq     configSDRAM
+
+    li      r6, 0xe0            /* error codes in r6 and r7  */
+    li      r7, 0x01
+    b       toggleError         /* fail - loop forever */
+
+configSDRAM:
+    addi    r3, r13, (MsdRam-MessageBlock)
+    bl      Printf
+/*
+ * set the Memory Configuration Reg. 1
+ */
+    li      r3, 0x001f          /* get bank size from spd bank0/1 */
+    bl      spdRead
+
+    andi.   r3, r3, 0x0038
+    beq     SD16MB2B
+
+    li      r3, 0x0011          /* get number of internal banks */
+				/* from spd for bank0/1 */
+    bl      spdRead
+
+    cmpli   0, 0, r3, 0x02
+    beq     SD64MB2B
+
+    cmpli   0, 0, r3, 0x04
+    beq     SD64MB4B
+
+    li      r6, 0xe0            /* error codes in r6 and r7  */
+    li      r7, 0x02
+    b       toggleError         /* fail - loop forever */
+
+SD64MB2B:
+    li      r20, 0x0005         /* 64-Mbit SDRAM 2 banks */
+    b       SDRow2nd
+
+SD64MB4B:
+    li      r20, 0x0000         /* 64-Mbit SDRAM 4 banks */
+    b       SDRow2nd
+
+SD16MB2B:
+    li      r20, 0x000f         /* 16-Mbit SDRAM 2 banks */
+
+SDRow2nd:
+    li      r3, 0x0102          /* get RAM type spd for bank2/3 */
+    bl      spdRead
+
+    cmpli   0, 0, r3, 0x0004
+    bne     S2D64MB4B           /* bank2/3 isn't present or no SDRAM */
+
+    li      r3, 0x011f          /* get bank size from spd bank2/3 */
+    bl      spdRead
+
+    andi.   r3, r3, 0x0038
+    beq     S2D16MB2B
+/*
+ * set the Memory Configuration Reg. 2
+ */
+    li      r3, 0x0111          /* get number of internal banks */
+				/* from spd for bank2/3 */
+    bl      spdRead
+
+    cmpli   0, 0, r3, 0x02
+    beq     S2D64MB2B
+
+    cmpli   0, 0, r3, 0x04
+    beq     S2D64MB4B
+
+    li      r6, 0xe0            /* error codes in r6 and r7 */
+    li      r7, 0x03
+    b       toggleError         /* fail - loop forever */
+
+S2D64MB2B:
+    ori     r20, r20, 0x0050    /* 64-Mbit SDRAM 2 banks */
+    b       S2D64MB4B
+
+S2D16MB2B:
+    ori     r20, r20, 0x00f0    /* 16-Mbit SDRAM 2 banks */
+
+/*
+ * set the Memory Configuration Reg. 3
+ */
+S2D64MB4B:
+    lis     r21, 0x8630         /* BSTOPRE = 0x80, REFREC = 6, */
+				/* RDLAT = 3 */
+
+/*
+ * set the Memory Configuration Reg. 4
+ */
+    lis     r22, 0x2430         /* PRETOACT = 2, ACTOPRE = 4, */
+				/* WCBUF = 1, RCBUF = 1 */
+    ori     r22, r22, 0x2220    /* SDMODE = 0x022, ACTORW = 2 */
+
+/*
+ * get the size of bank 0-3
+ */
+    li      r3, 0x001f          /* get bank size from spd bank0/1 */
+    bl      spdRead
+
+    rlwinm  r16, r3, 2, 24, 29  /* calculate size in MByte */
+				/* (128 MB max.) */
+
+    li      r3, 0x0005          /* get number of banks from spd */
+				/* for bank0/1 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, 2         /* 2 banks ? */
+    bne     SDRAMnobank1
+
+    mr      r17, r16
+
+SDRAMnobank1:
+    addi    r3, r13, (Mspd23-MessageBlock)
+    bl      Printf
+
+    li      r3, 0x0102          /* get RAM type spd for bank2/3 */
+    bl      spdRead
+
+    cmpli   0, 0, r3, 0x0001    /* FPM ? */
+    bne     noFPM23             /* handle as EDO */
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+    addi    r3, r13, (MfpmRam-MessageBlock)
+    bl      Printf
+    b       configRAMcommon
+noFPM23:
+    cmpli   0, 0, r3, 0x0002    /* EDO ? */
+    bne     noEDO23
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+    addi    r3, r13, (MedoRam-MessageBlock)
+    bl      Printf
+    b       configRAMcommon
+noEDO23:
+    cmpli   0, 0, r3, 0x0004    /* SDRAM ? */
+    bne    noSDRAM23
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+    addi    r3, r13, (MsdRam-MessageBlock)
+    bl      Printf
+    b       configSDRAM23
+noSDRAM23:
+    addi    r3, r13, (Mna-MessageBlock)
+    bl      Printf
+    b       configRAMcommon     /* bank2/3 isn't present or no SDRAM */
+
+configSDRAM23:
+    li      r3, 0x011f          /* get bank size from spd bank2/3 */
+    bl      spdRead
+
+    rlwinm  r18, r3, 2, 24, 29  /* calculate size in MByte */
+				/* (128 MB max.) */
+
+    li      r3, 0x0105          /* get number of banks from */
+				/* spd bank0/1 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, 2         /* 2 banks ? */
+    bne     SDRAMnobank3
+
+    mr    r19, r18
+
+SDRAMnobank3:
+    b       configRAMcommon
+
+configFPM:
+    addi    r3, r13, (MfpmRam-MessageBlock)
+    bl      Printf
+    b       configEDO0
+/*
+ * set the Memory Configuration Reg. 1
+ */
+configEDO:
+    addi    r3, r13, (MedoRam-MessageBlock)
+    bl      Printf
+configEDO0:
+    lis     r20, MCCR1_TYPE_EDO@h
+
+getSpdRowBank01:
+    li      r3, 0x0003          /* get number of row bits from */
+				/* spd from bank0/1 */
+    bl      spdRead
+    ori     r20, r20, (MCCR1_BK0_9BITS | MCCR1_BK1_9BITS)
+    cmpli   0, 0, r3, 0x0009    /* bank0 -  9 row bits */
+    beq     getSpdRowBank23
+
+    ori     r20, r20, (MCCR1_BK0_10BITS | MCCR1_BK1_10BITS)
+    cmpli   0, 0, r3, 0x000a    /* bank0 -  10 row bits */
+    beq     getSpdRowBank23
+
+    ori     r20, r20, (MCCR1_BK0_11BITS | MCCR1_BK1_11BITS)
+    cmpli   0, 0, r3, 0x000b    /* bank0 -  11 row bits */
+    beq     getSpdRowBank23
+
+    ori     r20, r20, (MCCR1_BK0_12BITS | MCCR1_BK1_12BITS)
+    cmpli   0, 0, r3, 0x000c    /* bank0 -  12 row bits */
+    beq     getSpdRowBank23
+
+    cmpli   0, 0, r3, 0x000d    /* bank0 -  13 row bits */
+    beq     getSpdRowBank23
+
+    li      r6, 0xe0            /* error codes in r6 and r7 */
+    li      r7, 0x10
+    b       toggleError         /* fail - loop forever */
+
+getSpdRowBank23:
+    li     r3, 0x0103           /* get number of row bits from */
+				/* spd for bank2/3 */
+    bl      spdRead
+
+    ori     r20, r20, (MCCR1_BK2_9BITS | MCCR1_BK3_9BITS)
+    cmpli   0, 0, r3, 0x0009    /* bank0 -  9 row bits */
+    beq     writeRowBits
+
+    ori     r20, r20, (MCCR1_BK2_10BITS | MCCR1_BK3_10BITS)
+    cmpli   0, 0, r3, 0x000a    /* bank0 -  10 row bits */
+    beq     writeRowBits
+
+    ori     r20, r20, (MCCR1_BK2_11BITS | MCCR1_BK3_11BITS)
+    cmpli   0, 0, r3, 0x000b    /* bank0 -  11 row bits */
+    beq     writeRowBits
+
+    ori     r20, r20, (MCCR1_BK2_12BITS | MCCR1_BK3_12BITS)
+
+/*
+ * set the Memory Configuration Reg. 3
+ */
+writeRowBits:
+    lis     r21, 0x000a         /* CPX = 1, RAS6P = 4 */
+    ori     r21, r21, 0x2293    /* CAS5 = 2, CP4 = 1, */
+				/* CAS3 = 2, RCD2 = 2, RP = 3 */
+/*
+ * set the Memory Configuration Reg. 4
+ */
+    lis     r22, 0x0010         /* all SDRAM parameter 0, */
+				/* WCBUF flow through, */
+				/* RCBUF registered */
+/*
+ * get the size of bank 0-3
+ */
+    li      r3, 0x0003          /* get row bits from spd  bank0/1 */
+    bl      spdRead
+
+    li      r16, 0              /* bank size is: */
+				/* (8*2^row*2^column)/0x100000 MB */
+    ori     r16, r16, 0x8000
+    rlwnm   r16, r16, r3, 0, 31
+
+    li      r3, 0x0004          /* get column bits from spd bank0/1 */
+    bl      spdRead
+
+    rlwnm   r16, r16, r3, 0, 31
+
+    li      r3, 0x0005          /* get number of banks from */
+				/* spd for bank0/1 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, 2         /* 2 banks ? */
+    bne     EDOnobank1
+
+    mr      r17, r16
+
+EDOnobank1:
+    addi    r3, r13, (Mspd23-MessageBlock)
+    bl      Printf
+
+    li      r3, 0x0102          /* get RAM type spd for bank2/3 */
+    bl      spdRead
+
+    cmpli   0, 0, r3, 0x0001    /* FPM ? */
+    bne     noFPM231            /* handle as EDO */
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+    addi    r3, r13, (MfpmRam-MessageBlock)
+    bl      Printf
+    b       EDObank2
+noFPM231:
+    cmpli   0, 0, r3, 0x0002    /* EDO ? */
+    bne     noEDO231
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+    addi    r3, r13, (MedoRam-MessageBlock)
+    bl      Printf
+    b       EDObank2
+noEDO231:
+    cmpli   0, 0, r3, 0x0004    /* SDRAM ? */
+    bne     noSDRAM231
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+    addi    r3, r13, (MsdRam-MessageBlock)
+    bl      Printf
+    b       configRAMcommon
+noSDRAM231:
+    addi    r3, r13, (Mfail-MessageBlock)
+    bl      Printf
+    b       configRAMcommon     /* bank2/3 isn't present or no SDRAM */
+
+EDObank2:
+    li      r3, 0x0103          /* get row bits from spd for bank2/3 */
+    bl      spdRead
+
+    li      r18, 0              /* bank size is: */
+				/* (8*2^row*2^column)/0x100000 MB */
+    ori     r18, r18, 0x8000
+    rlwnm   r18, r18, r3, 0, 31
+
+    li      r3, 0x0104          /* get column bits from spd bank2/3 */
+    bl      spdRead
+
+    rlwnm   r18, r18, r3, 0, 31
+
+    li      r3, 0x0105          /* get number of banks from */
+				/* spd for bank2/3 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, 2         /* 2 banks ? */
+    bne     configRAMcommon
+
+    mr      r19, r18
+
+configRAMcommon:
+    lis     r1, MPC106_REG_ADDR@h
+    ori     r1, r1, MPC106_REG_ADDR@l
+    lis     r2, MPC106_REG_DATA@h
+    ori     r2, r2, MPC106_REG_DATA@l
+
+    li      r0, 0
+
+/*
+ * If we are already running in RAM (debug mode), we should
+ * NOT reset the MEMGO flag. Otherwise we will stop all memory
+ * accesses.
+ */
+#ifdef IN_RAM
+    lis     r4, MCCR1_MEMGO@h
+    ori     r4, r4, MCCR1_MEMGO@l
+    or      r20, r20, r4
+#endif
+
+/*
+ * set the Memory Configuration Reg. 1
+ */
+    lis     r3, MPC106_REG@h        /* start building new reg number */
+    ori     r3, r3, MPC106_MCCR1    /* register number 0xf0 */
+    stwbrx  r3, r0, r1              /* write this value to CONFIG_ADDR */
+    eieio                           /* make sure mem. access is complete */
+    stwbrx  r20, r0, r2             /* write data to CONFIG_DATA */
+/*
+ * set the Memory Configuration Reg. 3
+ */
+    lis     r3, MPC106_REG@h        /* start building new reg number */
+    ori     r3, r3, MPC106_MCCR3    /* register number 0xf8 */
+    stwbrx  r3, r0, r1              /* write this value to CONFIG_ADDR */
+    eieio                           /* make sure mem. access is complete */
+    stwbrx    r21, r0, r2           /* write data to CONFIG_DATA */
+/*
+ * set the Memory Configuration Reg. 4
+ */
+    lis     r3, MPC106_REG@h        /* start building new reg number */
+    ori     r3, r3, MPC106_MCCR4    /* register number 0xfc */
+    stwbrx  r3, r0, r1              /* write this value to CONFIG_ADDR */
+    eieio                           /* make sure mem. access is complete */
+    stwbrx  r22, r0, r2             /* write data to CONFIG_DATA */
+/*
+ * set the memory boundary registers for bank 0-3
+ */
+    li      r20, 0
+    li      r23, 0
+    li      r24, 0
+    subi    r21, r16, 1         /* calculate end address bank0 */
+    li      r22, (MBER_BANK0)
+
+    cmpi    0, 0, r17, 0        /* bank1 present ? */
+    beq     nobank1
+
+    rlwinm  r3, r16, 8, 16, 23  /* calculate start address of bank1 */
+    or      r20, r20, r3
+    add     r16, r16, r17       /* add to total memory size */
+    subi    r3, r16, 1          /* calculate end address of bank1 */
+    rlwinm  r3, r3, 8, 16, 23
+    or      r21, r21, r3
+    ori     r22, r22, (MBER_BANK1)      /* enable bank1 */
+    b       bank2
+
+nobank1:
+    ori     r23, r23, 0x0300    /* set bank1 start to unused area */
+    ori     r24, r24, 0x0300    /* set bank1 end to unused area */
+
+bank2:
+    cmpi    0, 0, r18, 0        /* bank2 present ? */
+    beq     nobank2
+
+    andi.   r3, r16, 0x00ff     /* calculate start address of bank2 */
+    andi.   r4, r16, 0x0300
+    rlwinm  r3, r3, 16, 8, 15
+    or      r20, r20, r3
+    rlwinm  r3, r4, 8, 8, 15
+    or      r23, r23, r3
+    add     r16, r16, r18       /* add to total memory size */
+    subi    r3, r16, 1          /* calculate end address of bank2 */
+    andi.   r4, r3, 0x0300
+    andi.   r3, r3, 0x00ff
+    rlwinm  r3, r3, 16, 8, 15
+    or      r21, r21, r3
+    rlwinm  r3, r4, 8, 8, 15
+    or      r24, r24, r3
+    ori     r22, r22, (MBER_BANK2)    /* enable bank2 */
+    b       bank3
+
+nobank2:
+    lis     r3, 0x0003
+    or      r23, r23, r3        /* set bank2 start to unused area */
+    or      r24, r24, r3        /* set bank2 end to unused area */
+
+bank3:
+    cmpi    0, 0, r19, 0        /* bank3 present ? */
+    beq     nobank3
+
+    andi.   r3, r16, 0x00ff     /* calculate start address of bank3 */
+    andi.   r4, r16, 0x0300
+    rlwinm  r3, r3, 24, 0, 7
+    or      r20, r20, r3
+    rlwinm  r3, r4, 16, 0, 7
+    or      r23, r23, r3
+    add     r16, r16, r19       /* add to total memory size */
+    subi    r3, r16, 1          /* calculate end address of bank3 */
+    andi.   r4, r3, 0x0300
+    andi.   r3, r3, 0x00ff
+    rlwinm  r3, r3, 24, 0, 7
+    or      r21, r21, r3
+    rlwinm  r3, r4, 16, 0, 7
+    or      r24, r24, r3
+    ori     r22, r22, (MBER_BANK3)    /* enable bank3 */
+    b       writebound
+
+nobank3:
+    lis     r3, 0x0300
+    or      r23, r23, r3        /* set bank3 start to unused area */
+    or      r24, r24, r3        /* set bank3 end to unused area */
+
+writebound:
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_MSAR1    /* register number 0x80 */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+    stwbrx  r20, r0, r2         /* write data to CONFIG_DATA */
+
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_MEAR1    /* register number 0x90 */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+    stwbrx  r21, r0, r2         /* write data to CONFIG_DATA */
+
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_EMSAR1    /* register number 0x88 */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+    stwbrx  r23, r0, r2         /* write data to CONFIG_DATA */
+
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_EMEAR1    /* register number 0x98 */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+    stwbrx  r24, r0, r2         /* write data to CONFIG_DATA */
+
+/*
+ * set boundaries of unused banks to unused address space
+ */
+    lis     r4, 0x0303
+    ori     r4, r4, 0x0303      /* bank 4-7 start and end adresses */
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_EMSAR2    /* register number 0x8C */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+    stwbrx  r4, r0, r2          /* write data to CONFIG_DATA */
+
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_EMEAR2    /* register number 0x9C */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+    stwbrx  r4, r0, r2          /* write data to CONFIG_DATA */
+
+/*
+ * set the Memory Configuration Reg. 2
+ */
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_MCCR2    /* register number 0xf4 */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+
+    li      r3, 0x000c          /* get refresh from spd for bank0/1 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, -1        /* error ? */
+    bne     common1
+
+    li      r6, 0xe0            /* error codes in r6 and r7  */
+    li      r7, 0x20
+    b       toggleError         /* fail - loop forever */
+
+common1:
+    andi.   r15, r3, 0x007f     /* mask selfrefresh bit */
+    li      r3, 0x010c          /* get refresh from spd for bank2/3 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, -1        /* error ? */
+    beq     common2
+    andi.   r3, r3, 0x007f      /* mask selfrefresh bit */
+    cmp     0, 0, r3, r15       /* find the lower */
+    blt     common3
+
+common2:
+    mr      r3, r15
+
+common3:
+    li      r4, 0x1010          /* refesh cycle 1028 clocks */
+				/*  left shifted 2 */
+    cmpli   0, 0, r3, 0x0000    /* 15.6 us ? */
+    beq     writeRefresh
+
+    li      r4, 0x0808          /* refesh cycle 514 clocks */
+				/* left shifted 2 */
+    cmpli   0, 0, r3, 0x0002    /* 7.8 us ? */
+    beq     writeRefresh
+
+    li      r4, 0x2020          /* refesh cycle 2056 clocks */
+				/* left shifted 2 */
+    cmpli   0, 0, r3, 0x0003    /* 31.3 us ? */
+    beq     writeRefresh
+
+    li      r4, 0x4040          /* refesh cycle 4112 clocks */
+				/* left shifted 2 */
+    cmpli   0, 0, r3, 0x0004    /* 62.5 us ? */
+    beq     writeRefresh
+
+    li      r4, 0
+    ori     r4, r4, 0x8080      /* refesh cycle 8224 clocks */
+				/* left shifted 2 */
+    cmpli   0, 0, r3, 0x0005    /* 125 us ? */
+    beq     writeRefresh
+
+    li      r6, 0xe0            /* error codes in r6 and r7 */
+    li      r7, 0x21
+    b       toggleError         /* fail - loop forever */
+
+writeRefresh:
+    stwbrx  r4, r0, r2          /* write data to CONFIG_DATA */
+
+/*
+ * DRAM BANKS SHOULD BE ENABLED
+ */
+    addi    r3, r13, (Mactivate-MessageBlock)
+    bl      Printf
+    mr      r3, r16
+    bl      OutDec
+    addi    r3, r13, (Mmbyte-MessageBlock)
+    bl      Printf
+
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_MBER /* register number 0xa0 */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+    stb     r22, 0(r2)          /* write data to CONFIG_DATA */
+    li      r8, 0x63            /* PGMAX = 99 */
+    stb     r8, 3(r2)           /* write data to CONFIG_DATA */
+
+/*
+ *  DRAM SHOULD NOW BE CONFIGURED AND ENABLED
+ *  MUST WAIT 200us BEFORE ACCESSING
+ */
+    li      r0, 0x7800
+    mtctr   r0
+
+wait200us:
+    bdnz    wait200us
+
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_MCCR1    /* register number 0xf0 */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+
+    lwbrx   r4, r0, r2          /* load r4 from CONFIG_DATA */
+
+    lis     r0, MCCR1_MEMGO@h   /* MEMGO=1 */
+    ori     r0, r0, MCCR1_MEMGO@l
+    or      r4, r4, r0          /* set the MEMGO bit */
+    stwbrx  r4, r0, r2          /* write mdfd data to CONFIG_DATA */
+
+    li      r0, 0x7000
+    mtctr   r0
+
+wait8ref:
+    bdnz    wait8ref
+
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+
+    mtlr    r25
+    blr
+
+/*
+ * Infinite loop called in case of an error during RAM initialisation.
+ * error codes in r6 and r7.
+ */
+toggleError:
+    li      r0, 0
+    lis     r9, 127
+    ori     r9, r9, 65535
+toggleError1:
+    addic   r0, r0, 1
+    cmpw    cr1, r0, r9
+    ble     cr1, toggleError1
+    li      r0, 0
+    lis     r9, 127
+    ori     r9, r9, 65535
+toggleError2:
+    addic   r0, r0, 1
+    cmpw    cr1, r0, r9
+    ble     cr1, toggleError2
+    b       toggleError
+
+
+/******************************************************************************
+ * This function performs a basic initialisation of the superio chip
+ * to enable basic console output and SPD access during RAM initialisation.
+ *
+ * Upon completion, SIO resource registers are mapped as follows:
+ * Resource     Enabled         Address
+ * UART1        Yes             3F8-3FF COM1
+ * UART2        Yes             2F8-2FF COM2
+ * GPIO         Yes             220-227
+ */
+.set    SIO_LUNINDEX, 0x07      /* SIO LUN index register */
+.set    SIO_CNFG1, 0x21         /* SIO configuration #1 register */
+.set    SIO_PCSCI, 0x23         /* SIO PCS configuration index reg */
+.set    SIO_PCSCD, 0x24         /* SIO PCS configuration data reg */
+.set    SIO_ACTIVATE, 0x30      /* SIO activate register */
+.set    SIO_IOBASEHI, 0x60      /* SIO I/O port base address, 15:8 */
+.set    SIO_IOBASELO, 0x61      /* SIO I/O port base address, 7:0 */
+.set    SIO_LUNENABLE, 0x01     /* SIO LUN enable */
+
+.sioInit:
+    mfspr   r7, 8               /* save link register */
+
+.sioInit_87308:
+
+/*
+ * Get base addr of ISA I/O space
+ */
+    lis     r6, CFG_ISA_IO@h
+    ori     r6, r6, CFG_ISA_IO@l
+
+/*
+ * Set offset to base address for config registers.
+ */
+#if defined(CFG_NS87308_BADDR_0x)
+    addi    r4, r0, 0x0279
+#elif defined(CFG_NS87308_BADDR_10)
+    addi    r4, r0, 0x015C
+#elif defined(CFG_NS87308_BADDR_11)
+    addi    r4, r0, 0x002E
+#endif
+    add     r6, r6, r4          /* add offset to base */
+    or      r3, r6, r6          /* make a copy */
+
+/*
+ * PMC (LUN 8)
+ */
+    addi    r4, r0, SIO_LUNINDEX    /* select PMC LUN */
+    addi    r5, r0, 0x8
+    bl      .sio_bw
+    addi    r4, r0, SIO_IOBASEHI    /* initialize PMC address to 0x460 */
+    addi    r5, r0, 0x04
+    bl      .sio_bw
+    addi    r4, r0, SIO_IOBASELO
+    addi    r5, r0, 0x60
+    bl      .sio_bw
+    addi    r4, r0, SIO_ACTIVATE    /* enable PMC */
+    addi    r5, r0, SIO_LUNENABLE
+    bl      .sio_bw
+
+    lis     r8, CFG_ISA_IO@h
+    ori     r8, r8, 0x0460
+    li      r9, 0x03
+    stb     r9, 0(r8)               /* select PMC2 register */
+    eieio
+    li      r9, 0x00
+    stb     r9, 1(r8)               /* SuperI/O clock src: 24MHz via X1 */
+    eieio
+
+/*
+ * map UART1 (LUN 6) or UART2 (LUN 5) to COM1 (0x3F8)
+ */
+    addi    r4, r0, SIO_LUNINDEX    /* select COM1 LUN */
+    addi    r5, r0, 0x6
+    bl      .sio_bw
+
+    addi    r4, r0, SIO_IOBASEHI    /* initialize COM1 address to 0x3F8 */
+    addi    r5, r0, 0x03
+    bl      .sio_bw
+
+    addi    r4, r0, SIO_IOBASELO
+    addi    r5, r0, 0xF8
+    bl      .sio_bw
+
+    addi    r4, r0, SIO_ACTIVATE    /* enable COM1 */
+    addi    r5, r0, SIO_LUNENABLE
+    bl      .sio_bw
+
+/*
+ * Init COM1 for polled output
+ */
+    lis     r8, CFG_ISA_IO@h
+    ori     r8, r8, 0x03f8
+    li      r9, 0x00
+    stb     r9, 1(r8)           /* int disabled */
+    eieio
+    li      r9, 0x00
+    stb     r9, 4(r8)           /* modem ctrl */
+    eieio
+    li      r9, 0x80
+    stb     r9, 3(r8)           /* link ctrl, bank select */
+    eieio
+    li      r9, 115200/CONFIG_BAUDRATE
+    stb     r9, 0(r8)           /* baud rate (LSB)*/
+    eieio
+    rotrwi  r9, r9, 8
+    stb     r9, 1(r8)           /* baud rate (MSB) */
+    eieio
+    li      r9, 0x03
+    stb     r9, 3(r8)           /* 8 data bits, 1 stop bit, */
+				/* no parity */
+    eieio
+    li      r9, 0x0b
+    stb     r9, 4(r8)           /* enable the receiver and transmitter */
+    eieio
+
+waitEmpty:
+    lbz     r9, 5(r8)           /* transmit empty */
+    andi.   r9, r9, 0x40
+    beq     waitEmpty
+    li      r9, 0x47
+    stb     r9, 3(r8)           /* send break, 8 data bits, */
+				/* 2 stop bits, no parity */
+    eieio
+
+    lis     r0, 0x0001
+    mtctr   r0
+
+waitCOM1:
+    lwz     r0, 5(r8)           /* load from port for delay */
+    bdnz    waitCOM1
+
+waitEmpty1:
+    lbz     r9, 5(r8)           /* transmit empty */
+    andi.   r9, r9, 0x40
+    beq     waitEmpty1
+    li      r9, 0x07
+    stb     r9, 3(r8)           /* 8 data bits, 2 stop bits, */
+				/* no parity */
+    eieio
+
+/*
+ * GPIO (LUN 7)
+ */
+    addi    r4, r0, SIO_LUNINDEX    /* select GPIO LUN */
+    addi    r5, r0, 0x7
+    bl      .sio_bw
+
+    addi    r4, r0, SIO_IOBASEHI    /* initialize GPIO address to 0x220 */
+    addi    r5, r0, 0x02
+    bl      .sio_bw
+
+    addi    r4, r0, SIO_IOBASELO
+    addi    r5, r0, 0x20
+    bl      .sio_bw
+
+    addi    r4, r0, SIO_ACTIVATE    /* enable GPIO */
+    addi    r5, r0, SIO_LUNENABLE
+    bl      .sio_bw
+
+.sioInit_done:
+
+/*
+ * Get base addr of ISA I/O space
+ */
+    lis     r3, CFG_ISA_IO@h
+    ori     r3, r3, CFG_ISA_IO@l
+
+    addi    r3, r3, 0x015C      /* adjust to superI/O 87308 base */
+    or      r6, r3, r3          /* make a copy */
+/*
+ * CS0
+ */
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x00
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x00
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x01
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x76
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x02
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x40
+    bl      .sio_bw
+/*
+ * CS1
+ */
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x05
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x00
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x05
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x70
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x06
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x1C
+    bl      .sio_bw
+/*
+ * CS2
+ */
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x08
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x00
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x09
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x71
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x0A
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x1C
+    bl      .sio_bw
+
+    mtspr   8, r7               /* restore link register */
+    bclr    20, 0               /* return to caller */
+
+/*
+ * this function writes a register to the SIO chip
+ */
+.sio_bw:
+    stb     r4, 0(r3)           /* write index register with register offset */
+    eieio
+    sync
+    stb     r5, 1(r3)           /* 1st write */
+    eieio
+    sync
+    stb     r5, 1(r3)           /* 2nd write */
+    eieio
+    sync
+    bclr    20, 0               /* return to caller */
+/*
+ * this function reads a register from the SIO chip
+ */
+.sio_br:
+    stb     r4, 0(r3)           /* write index register with register offset */
+    eieio
+    sync
+    lbz     r3, 1(r3)           /* retrieve specified reg offset contents */
+    eieio
+    sync
+    bclr    20, 0               /* return to caller */
+
+/*
+ * Print a message to COM1 in polling mode
+ * r10=COM1 port, r3=(char*)string
+ */
+.globl Printf
+Printf:
+    lis     r10, CFG_ISA_IO@h   /* COM1 port */
+    ori     r10, r10, 0x03f8
+
+WaitChr:
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, WaitChr        /* wait till empty */
+    lbzx    r0, r0, r3          /* get char */
+    stb     r0, 0(r10)          /* write to transmit reg */
+    eieio
+    addi    r3, r3, 1           /* next char */
+    lbzx    r0, r0, r3          /* get char */
+    cmpwi   cr1, r0, 0          /* end of string ? */
+    bne     cr1, WaitChr
+    blr
+
+/*
+ * Print 8/4/2 digits hex value to COM1 in polling mode
+ * r10=COM1 port, r3=val
+ */
+OutHex2:
+    li      r9, 4               /* shift reg for 2 digits */
+    b       OHstart
+OutHex4:
+    li      r9, 12              /* shift reg for 4 digits */
+    b       OHstart
+    .globl OutHex
+OutHex:
+    li      r9, 28              /* shift reg for 8 digits */
+OHstart:
+    lis     r10, CFG_ISA_IO@h   /* COM1 port */
+    ori     r10, r10, 0x03f8
+OutDig:
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutDig
+    sraw    r0, r3, r9
+    clrlwi  r0, r0, 28
+    cmpwi   cr1, r0, 9
+    ble     cr1, digIsNum
+    addic   r0, r0, 55
+    b       nextDig
+digIsNum:
+    addic   r0, r0, 48
+nextDig:
+    stb     r0, 0(r10)          /* write to transmit reg */
+    eieio
+    addic.  r9, r9, -4
+    bge     OutDig
+    blr
+/*
+ * Print 3 digits hdec value to COM1 in polling mode
+ * r10=COM1 port, r3=val, r7=x00, r8=x0, r9=x, r0, r6=scratch
+ */
+.globl OutDec
+OutDec:
+    li      r6, 10
+    divwu   r0, r3, r6          /* r0 = r3 / 10, r9 = r3 mod 10 */
+    mullw   r10, r0, r6
+    subf    r9, r10, r3
+
+    mr      r3, r0
+    divwu   r0, r3, r6          /* r0 = r3 / 10, r8 = r3 mod 10 */
+    mullw   r10, r0, r6
+    subf    r8, r10, r3
+
+    mr      r3, r0
+    divwu   r0, r3, r6          /* r0 = r3 / 10, r7 = r3 mod 10 */
+    mullw   r10, r0, r6
+    subf    r7, r10, r3
+
+    lis     r10, CFG_ISA_IO@h   /* COM1 port */
+    ori     r10, r10, 0x03f8
+
+    or.     r7, r7, r7
+    bne     noblank1
+    li      r3, 0x20
+    b       OutDec4
+
+noblank1:
+    addi    r3, r7, 48          /* convert to ASCII */
+
+OutDec4:
+    lbz     r0, 0(r13)          /* slow down dummy read */
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutDec4
+    stb     r3, 0(r10)          /* x00 to transmit */
+    eieio
+
+    or.     r7, r7, r8
+    beq     OutDec5
+
+    addi    r3, r8, 48          /* convert to ASCII */
+OutDec5:
+    lbz     r0, 0(r13)          /* slow down dummy read */
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutDec5
+    stb     r3, 0(r10)          /* x0  to transmit */
+    eieio
+
+    addi    r3, r9, 48          /* convert to ASCII */
+OutDec6:
+    lbz     r0, 0(r13)          /* slow down dummy read */
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutDec6
+    stb     r3, 0(r10)          /* x   to transmit */
+    eieio
+    blr
+/*
+ * Print a char to COM1 in polling mode
+ * r10=COM1 port, r3=char
+ */
+.globl    OutChr
+OutChr:
+    lis     r10, CFG_ISA_IO@h   /* COM1 port */
+    ori     r10, r10, 0x03f8
+
+OutChr1:
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutChr1        /* wait till empty */
+    stb     r3, 0(r10)          /* write to transmit reg */
+    eieio
+    blr
+/*
+ * Input:  r3 adr to read
+ * Output: r3 val or -1 for error
+ */
+spdRead:
+    mfspr   r26, 8              /* save link register */
+
+    lis     r30, CFG_ISA_IO@h
+    ori     r30, r30, 0x220     /* GPIO Port 1 */
+    li      r7, 0x00
+    li      r8, 0x100
+    and.    r5, r3, r8
+    beq     spdbank0
+    li      r12, 0x08
+    li      r4, 0x10
+    li      r6, 0x18
+    b       spdRead1
+
+spdbank0:
+    li      r12, 0x20           /* set I2C data */
+    li      r4, 0x40            /* set I2C clock */
+    li      r6, 0x60            /* set I2C clock and data */
+
+spdRead1:
+    li      r8, 0x80
+
+    bl      spdStart            /* access I2C bus as master */
+    li      r10, 0xa0           /* write to SPD */
+    bl      spdWriteByte
+    bl      spdReadAck          /* ACK returns in r10 */
+    cmpw    cr0, r10, r7
+    bne     AckErr              /* r10 must be 0, if ACK received */
+    mr      r10, r3             /* adr to read */
+    bl      spdWriteByte
+    bl      spdReadAck
+    cmpw    cr0, r10, r7
+    bne     AckErr
+    bl      spdStart
+    li      r10, 0xa1           /* read from SPD */
+    bl      spdWriteByte
+    bl      spdReadAck
+    cmpw    cr0, r10, r7
+    bne     AckErr
+    bl      spdReadByte         /* return val in r10 */
+    bl      spdWriteAck
+    bl      spdStop             /* release I2C bus */
+    mr      r3, r10
+    mtspr   8, r26              /* restore link register */
+    blr
+/*
+ * ACK error occurred
+ */
+AckErr:
+    bl      spdStop
+    orc     r3, r0, r0          /* return -1 */
+    mtspr   8, r26              /* restore link register */
+    blr
+
+/*
+ * Routines to read from RAM spd.
+ * r30 - GPIO Port1 address in all cases.
+ * r4 - clock mask for SPD
+ * r6 - port mask for SPD
+ * r12 - data mask for SPD
+ */
+waitSpd:
+    li      r0, 0x1000
+    mtctr   r0
+wSpd:
+    bdnz    wSpd
+    bclr    20, 0               /* return to caller */
+
+/*
+ * establish START condition on I2C bus
+ */
+spdStart:
+    mfspr   r27, 8              /* save link register */
+    stb     r6, 0(r30)          /* set SDA and SCL */
+    eieio
+    stb     r6, 1(r30)          /* switch GPIO to output */
+    eieio
+    bl      waitSpd
+    stb     r4, 0(r30)          /* reset SDA */
+    eieio
+    bl      waitSpd
+    stb     r7, 0(r30)          /* reset SCL */
+    eieio
+    bl      waitSpd
+    mtspr   8, r27
+    bclr    20, 0               /* return to caller */
+
+/*
+ * establish STOP condition on I2C bus
+ */
+spdStop:
+    mfspr   r27, 8              /* save link register */
+    stb     r7, 0(r30)          /* reset SCL and SDA */
+    eieio
+    stb     r6, 1(r30)          /* switch GPIO to output */
+    eieio
+    bl      waitSpd
+    stb     r4, 0(r30)          /* set SCL */
+    eieio
+    bl      waitSpd
+    stb     r6, 0(r30)          /* set SDA and SCL */
+    eieio
+    bl      waitSpd
+    stb     r7, 1(r30)          /* switch GPIO to input */
+    eieio
+    mtspr   8, r27
+    bclr    20, 0               /* return to caller */
+
+spdReadByte:
+    mfspr   r27, 8
+    stb     r4, 1(r30)          /* set GPIO for SCL output */
+    eieio
+    li      r9, 0x08
+    li      r10, 0x00
+loopRB:
+    stb     r7, 0(r30)          /* reset SDA and SCL */
+    eieio
+    bl      waitSpd
+    stb     r4, 0(r30)          /* set SCL */
+    eieio
+    bl      waitSpd
+    lbz     r5, 0(r30)          /* read from GPIO Port1 */
+    rlwinm  r10, r10, 1, 0, 31
+    and.    r5, r5, r12
+    beq     clearBit
+    ori     r10, r10, 0x01      /* append _1_ */
+clearBit:
+    stb     r7, 0(r30)          /* reset SCL */
+    eieio
+    bl      waitSpd
+    addic.  r9, r9, -1
+    bne     loopRB
+    mtspr   8, r27
+    bclr    20, 0               /* return (r10) to caller */
+
+/*
+ * spdWriteByte writes bits 24 - 31 of r10 to I2C.
+ * r8 contains bit mask 0x80
+ */
+spdWriteByte:
+    mfspr   r27, 8              /* save link register */
+    li      r9, 0x08            /* write octet */
+    and.    r5, r10, r8
+    bne     sWB1
+    stb     r7, 0(r30)          /* set SDA to _0_ */
+    eieio
+    b       sWB2
+sWB1:
+    stb     r12, 0(r30)         /* set SDA to _1_ */
+    eieio
+sWB2:
+    stb     r6, 1(r30)          /* set GPIO to output */
+    eieio
+loopWB:
+    and.    r5, r10, r8
+    bne     sWB3
+    stb     r7, 0(r30)          /* set SDA to _0_ */
+    eieio
+    b       sWB4
+sWB3:
+    stb     r12, 0(r30)         /* set SDA to _1_ */
+    eieio
+sWB4:
+    bl      waitSpd
+    and.    r5, r10, r8
+    bne     sWB5
+    stb     r4, 0(r30)          /* set SDA to _0_ and SCL */
+    eieio
+    b       sWB6
+sWB5:
+    stb     r6, 0(r30)          /* set SDA to _1_ and SCL */
+    eieio
+sWB6:
+    bl      waitSpd
+    and.    r5, r10, r8
+    bne     sWB7
+    stb     r7, 0(r30)          /* set SDA to _0_ and reset SCL */
+    eieio
+    b       sWB8
+sWB7:
+    stb     r12, 0(r30)         /* set SDA to _1_ and reset SCL */
+    eieio
+sWB8:
+    bl      waitSpd
+    rlwinm  r10, r10, 1, 0, 31  /* next bit */
+    addic.  r9, r9, -1
+    bne     loopWB
+    mtspr   8, r27
+    bclr    20, 0               /* return to caller */
+
+/*
+ * Read ACK from SPD, return value in r10
+ */
+spdReadAck:
+    mfspr   r27, 8              /* save link register */
+    stb     r4, 1(r30)          /* set GPIO to output */
+    eieio
+    stb     r7, 0(r30)          /* reset SDA and SCL */
+    eieio
+    bl      waitSpd
+    stb     r4, 0(r30)          /* set SCL */
+    eieio
+    bl      waitSpd
+    lbz     r10, 0(r30)         /* read GPIO Port 1 and mask SDA */
+    and     r10, r10, r12
+    bl      waitSpd
+    stb     r7, 0(r30)          /* reset SDA and SCL */
+    eieio
+    bl      waitSpd
+    mtspr   8, r27
+    bclr    20, 0               /* return (r10) to caller */
+
+spdWriteAck:
+    mfspr   r27, 8
+    stb     r12, 0(r30)         /* set SCL */
+    eieio
+    stb     r6, 1(r30)          /* set GPIO to output */
+    eieio
+    bl      waitSpd
+    stb     r6, 0(r30)          /* SDA and SCL */
+    eieio
+    bl      waitSpd
+    stb     r12, 0(r30)         /* reset SCL */
+    eieio
+    bl      waitSpd
+    mtspr   8, r27
+    bclr    20, 0               /* return to caller */
+
+get_lnk_reg:
+    mflr    r3                  /* return link reg */
+    blr
+
+/*
+ * Messages for console output
+ */
+.globl MessageBlock
+MessageBlock:
+Mok:
+    .ascii  "OK\015\012\000"
+Mfail:
+    .ascii  "FAILED\015\012\000"
+Mna:
+    .ascii  "NA\015\012\000"
+MinitLogo:
+    .ascii  "\015\012*** ELTEC Elektronik, Mainz ***\015\012"
+    .ascii  "\015\012Initialising RAM\015\012\000"
+Mspd01:
+    .ascii  "       Reading SPD of bank0/1 ..... \000"
+Mspd23:
+    .ascii  "       Reading SPD of bank2/3 ..... \000"
+MfpmRam:
+    .ascii  "       RAM-Type: FPM \015\012\000"
+MedoRam:
+    .ascii  "       RAM-Type: EDO \015\012\000"
+MsdRam:
+    .ascii  "       RAM-Type: SDRAM \015\012\000"
+Mactivate:
+    .ascii  "       Activating \000"
+Mmbyte:
+    .ascii  " MB .......... \000"
+    .align  4
diff --git a/board/eltec/bab7xx/bab7xx.c b/board/eltec/bab7xx/bab7xx.c
new file mode 100755
index 0000000..fc48ed5
--- /dev/null
+++ b/board/eltec/bab7xx/bab7xx.c
@@ -0,0 +1,246 @@
+/*
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+ * (C) Copyright 2001 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <mpc106.h>
+#include <mk48t59.h>
+#include <74xx_7xx.h>
+#include <ns87308.h>
+#include <video_fb.h>
+
+/*---------------------------------------------------------------------------*/
+/*
+ * Get Bus clock frequency
+ */
+ulong bab7xx_get_bus_freq (void)
+{
+	/*
+	 * The GPIO Port 1 on BAB7xx reflects the bus speed.
+	 */
+	volatile struct GPIO *gpio =
+		(struct GPIO *) (CFG_ISA_IO + CFG_NS87308_GPIO_BASE);
+
+	unsigned char data = gpio->dta1;
+
+	if (data & 0x02)
+		return 66666666;
+
+	return 83333333;
+}
+
+/*---------------------------------------------------------------------------*/
+
+/*
+ * Measure CPU clock speed (core clock GCLK1) (Approx. GCLK frequency in Hz)
+ */
+ulong bab7xx_get_gclk_freq (void)
+{
+	static const int pllratio_to_factor[] = {
+		00, 75, 70, 00, 20, 65, 100, 45, 30, 55, 40, 50, 80, 60, 35,
+			00,
+	};
+
+	return pllratio_to_factor[get_hid1 () >> 28] *
+		(bab7xx_get_bus_freq () / 10);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int checkcpu (void)
+{
+	uint pvr = get_pvr ();
+
+	printf ("MPC7xx V%d.%d", (pvr >> 8) & 0xFF, pvr & 0xFF);
+	printf (" at %ld / %ld MHz\n", bab7xx_get_gclk_freq () / 1000000,
+		bab7xx_get_bus_freq () / 1000000);
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int checkboard (void)
+{
+#ifdef CFG_ADDRESS_MAP_A
+	puts ("Board: ELTEC BAB7xx PReP\n");
+#else
+	puts ("Board: ELTEC BAB7xx CHRP\n");
+#endif
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int checkflash (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("2 MB ## Test not implemented yet ##\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+
+static unsigned int mpc106_read_cfg_dword (unsigned int reg)
+{
+	unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC);
+
+	out32r (MPC106_REG_ADDR, reg_addr);
+
+	return (in32r (MPC106_REG_DATA | (reg & 0x3)));
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int dram_size (int board_type)
+{
+	/* No actual initialisation to do - done when setting up
+	 * PICRs MCCRs ME/SARs etc in ram_init.S.
+	 */
+
+	register unsigned long i, msar1, mear1, memSize;
+
+#if defined(CFG_MEMTEST)
+	register unsigned long reg;
+
+	printf ("Testing DRAM\n");
+
+	/* write each mem addr with it's address */
+	for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4)
+		*reg = reg;
+
+	for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) {
+		if (*reg != reg)
+			return -1;
+	}
+#endif
+
+	/*
+	 * Since MPC106 memory controller chip has already been set to
+	 * control all memory, just read and interpret its memory boundery register.
+	 */
+	memSize = 0;
+	msar1 = mpc106_read_cfg_dword (MPC106_MSAR1);
+	mear1 = mpc106_read_cfg_dword (MPC106_MEAR1);
+	i = mpc106_read_cfg_dword (MPC106_MBER) & 0xf;
+
+	do {
+		if (i & 0x01)	/* is bank enabled ? */
+			memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1;
+		msar1 >>= 8;
+		mear1 >>= 8;
+		i >>= 1;
+	} while (i);
+
+	return (memSize * 0x100000);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	return dram_size (board_type);
+}
+
+/* ------------------------------------------------------------------------- */
+
+void after_reloc (ulong dest_addr)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/*
+	 * Jump to the main U-Boot board init code
+	 */
+	board_init_r ((gd_t *) gd, dest_addr);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * do_reset is done here because in this case it is board specific, since the
+ * 7xx CPUs can only be reset by external HW (the RTC in this case).
+ */
+void do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
+{
+#if defined(CONFIG_RTC_MK48T59)
+	/* trigger watchdog immediately */
+	rtc_set_watchdog (1, RTC_WD_RB_16TH);
+#else
+#error "You must define the macro CONFIG_RTC_MK48T59."
+#endif
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if defined(CONFIG_WATCHDOG)
+/*
+ * Since the 7xx CPUs don't have an internal watchdog, this function is
+ * board specific.  We use the RTC here.
+ */
+void watchdog_reset (void)
+{
+#if defined(CONFIG_RTC_MK48T59)
+	/* we use a 32 sec watchdog timer */
+	rtc_set_watchdog (8, RTC_WD_RB_4);
+#else
+#error "You must define the macro CONFIG_RTC_MK48T59."
+#endif
+}
+#endif /* CONFIG_WATCHDOG */
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+extern GraphicDevice smi;
+
+void video_get_info_str (int line_number, char *info)
+{
+	/* init video info strings for graphic console */
+	switch (line_number) {
+	case 1:
+		sprintf (info, " MPC7xx V%d.%d at %ld / %ld MHz",
+			 (get_pvr () >> 8) & 0xFF,
+			 get_pvr () & 0xFF,
+			 bab7xx_get_gclk_freq () / 1000000,
+			 bab7xx_get_bus_freq () / 1000000);
+		return;
+	case 2:
+		sprintf (info,
+			 " ELTEC BAB7xx with %ld MB DRAM and %ld MB FLASH",
+			 dram_size (0) / 0x100000, flash_init () / 0x100000);
+		return;
+	case 3:
+		sprintf (info, " %s", smi.modeIdent);
+		return;
+	}
+
+	/* no more info lines */
+	*info = 0;
+	return;
+}
+#endif
+
+/*---------------------------------------------------------------------------*/
diff --git a/board/eltec/bab7xx/config.mk b/board/eltec/bab7xx/config.mk
new file mode 100755
index 0000000..aa463c5
--- /dev/null
+++ b/board/eltec/bab7xx/config.mk
@@ -0,0 +1,26 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/eltec/bab7xx/dc_srom.c b/board/eltec/bab7xx/dc_srom.c
new file mode 100755
index 0000000..a44af6e
--- /dev/null
+++ b/board/eltec/bab7xx/dc_srom.c
@@ -0,0 +1,291 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * SRom I/O routines.
+ */
+
+#include <common.h>
+#include <pci.h>
+#include "srom.h"
+
+#define SROM_RD         0x00004000    /* Read from Boot ROM */
+#define SROM_WR         0x00002000    /* Write to Boot ROM */
+#define SROM_SR         0x00000800    /* Select Serial ROM when set */
+
+#define DT_IN           0x00000004    /* Serial Data In */
+#define DT_CLK          0x00000002    /* Serial ROM Clock */
+#define DT_CS           0x00000001    /* Serial ROM Chip Select */
+
+static u_int         dc_srom_iobase;
+
+/*----------------------------------------------------------------------------*/
+
+static int inl(u_long addr)
+{
+    return le32_to_cpu(*(volatile u_long *)(addr));
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void outl (int command, u_long addr)
+{
+    *(volatile u_long *)(addr) = cpu_to_le32(command);
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void sendto_srom(u_int command, u_long addr)
+{
+    outl(command, addr);
+    udelay(1);
+
+    return;
+}
+
+/*----------------------------------------------------------------------------*/
+
+static int getfrom_srom(u_long addr)
+{
+    s32 tmp;
+
+    tmp = inl(addr);
+    udelay(1);
+
+    return tmp;
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void srom_latch (u_int command, u_long addr)
+{
+    sendto_srom (command, addr);
+    sendto_srom (command | DT_CLK, addr);
+    sendto_srom (command, addr);
+
+    return;
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void srom_command_rd (u_int command, u_long addr)
+{
+    srom_latch (command, addr);
+    srom_latch (command, addr);
+    srom_latch ((command & 0x0000ff00) | DT_CS, addr);
+
+    return;
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void srom_command_wr (u_int command, u_long addr)
+{
+    srom_latch (command, addr);
+    srom_latch ((command & 0x0000ff00) | DT_CS, addr);
+    srom_latch (command, addr);
+
+    return;
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void srom_address(u_int command, u_long addr, u_char offset)
+{
+    int i;
+    signed char a;
+
+    a = (char)(offset << 2);
+    for (i=0; i<6; i++, a <<= 1)
+    {
+	srom_latch(command | ((a < 0) ? DT_IN : 0), addr);
+    }
+    udelay(1);
+
+    i = (getfrom_srom(addr) >> 3) & 0x01;
+
+    return;
+}
+/*----------------------------------------------------------------------------*/
+
+static short srom_data_rd (u_int command, u_long addr)
+{
+    int i;
+    short word = 0;
+    s32 tmp;
+
+    for (i=0; i<16; i++)
+    {
+	sendto_srom(command  | DT_CLK, addr);
+	tmp = getfrom_srom(addr);
+	sendto_srom(command, addr);
+
+	word = (word << 1) | ((tmp >> 3) & 0x01);
+    }
+
+    sendto_srom(command & 0x0000ff00, addr);
+
+    return word;
+}
+
+/*----------------------------------------------------------------------------*/
+
+static int srom_data_wr (u_int command, u_long addr, short val)
+{
+    int i;
+    u_long longVal;
+    s32 tmp;
+
+    longVal = (u_long)(le16_to_cpu(val));
+
+    for (i=0; i<16; i++)
+    {
+	tmp = (longVal & 0x8000)>>13;
+
+	sendto_srom (tmp | command, addr);
+	sendto_srom (tmp | command  | DT_CLK, addr);
+	sendto_srom (tmp | command, addr);
+
+	longVal = longVal<<1;
+    }
+
+    sendto_srom(command & 0x0000ff00, addr);
+    sendto_srom(command, addr);
+
+    tmp = 100;
+    do
+    {
+	if ((getfrom_srom(dc_srom_iobase) & 0x8) == 0x8)
+	    break;
+	udelay(1000);
+    } while (--tmp);
+
+    if (tmp == 0)
+    {
+	printf("Write DEC21143 SRom timed out !\n");
+	return (-1);
+    }
+
+    return 0;
+}
+
+
+/*----------------------------------------------------------------------------*/
+static short srom_rd (u_long addr, u_char offset)
+{
+    sendto_srom (SROM_RD | SROM_SR, addr);
+    srom_latch (SROM_RD | SROM_SR | DT_CS, addr);
+
+    srom_command_rd (SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
+
+    srom_address (SROM_RD | SROM_SR | DT_CS, addr, offset);
+
+    return srom_data_rd (SROM_RD | SROM_SR | DT_CS, addr);
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void srom_wr_enable (u_long addr)
+{
+    int i;
+
+    sendto_srom (SROM_WR | SROM_SR, addr);
+    srom_latch (SROM_WR | SROM_SR | DT_CS, addr);
+
+    srom_latch (SROM_WR | SROM_SR | DT_IN | DT_CS, addr);
+    srom_latch (SROM_WR | SROM_SR | DT_CS, addr);
+    srom_latch (SROM_WR | SROM_SR | DT_CS, addr);
+
+    for (i=0; i<6; i++)
+    {
+	srom_latch (SROM_WR | SROM_SR | DT_IN | DT_CS, addr);
+    }
+}
+
+/*----------------------------------------------------------------------------*/
+
+static int srom_wr (u_long addr, u_char offset, short val)
+{
+    srom_wr_enable (addr);
+
+    sendto_srom (SROM_WR | SROM_SR, addr);
+    srom_latch (SROM_WR | SROM_SR | DT_CS, addr);
+
+    srom_command_wr (SROM_WR | SROM_SR | DT_IN | DT_CS, addr);
+
+    srom_address (SROM_WR | SROM_SR | DT_CS, addr, offset);
+
+    return srom_data_wr (SROM_WR | SROM_SR | DT_CS, addr, val);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * load data from the srom
+ */
+int dc_srom_load (u_short *dest)
+{
+    int offset;
+    short tmp;
+
+    /* get srom iobase from local network controller */
+    pci_read_config_dword(PCI_BDF(0,14,0), PCI_BASE_ADDRESS_1, &dc_srom_iobase);
+    dc_srom_iobase &= PCI_BASE_ADDRESS_MEM_MASK;
+    dc_srom_iobase  = pci_mem_to_phys(PCI_BDF(0,14,0), dc_srom_iobase);
+    dc_srom_iobase += 0x48;            /* io offset for srom access */
+
+    memset (dest, 0, 128);
+    for (offset=0; offset<64; offset++)
+    {
+	tmp = srom_rd (dc_srom_iobase, offset);
+	*dest++ = le16_to_cpu(tmp);
+    }
+
+    return (0);
+}
+
+/*----------------------------------------------------------------------------*/
+
+/*
+ * store data into the srom
+ */
+int dc_srom_store (u_short *src)
+{
+    int offset;
+
+    /* get srom iobase from local network controller */
+    pci_read_config_dword(PCI_BDF(0,14,0), PCI_BASE_ADDRESS_1, &dc_srom_iobase);
+    dc_srom_iobase &= PCI_BASE_ADDRESS_MEM_MASK;
+    dc_srom_iobase  = pci_mem_to_phys(PCI_BDF(0,14,0), dc_srom_iobase);
+    dc_srom_iobase += 0x48;            /* io offset for srom access */
+
+    for (offset=0; offset<64; offset++)
+    {
+	if (srom_wr (dc_srom_iobase, offset, *src) == -1)
+		return (-1);
+	src++;
+    }
+
+    return (0);
+}
+
+/*----------------------------------------------------------------------------*/
diff --git a/board/eltec/bab7xx/el_srom.c b/board/eltec/bab7xx/el_srom.c
new file mode 100755
index 0000000..73f8066
--- /dev/null
+++ b/board/eltec/bab7xx/el_srom.c
@@ -0,0 +1,292 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "srom.h"
+
+/*----------------------------------------------------------------------------*/
+/*
+ *  START sequence
+ *        _ _________
+ *  SCLK  _>         \____
+ *        _ ____
+ *  SDIO  _>    \_________
+ *         :    :    :
+ */
+static void eepStart (void)
+{
+    out8(I2C_BUS_DAT, 0x60);     /* SCLK = high  SDIO = high */
+    out8(I2C_BUS_DIR, 0x60);     /* set output direction for SCLK/SDIO */
+    udelay(10);
+    out8(I2C_BUS_DAT, 0x40);     /* SCLK = high  SDIO = low */
+    udelay(10);
+    out8(I2C_BUS_DAT, 0x00);     /* SCLK = low   SDIO = low */
+    udelay(10);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ *  STOP sequence
+ *              _______
+ *  SCLK  _____/
+ *        _         ___
+ *  SDIO  _>_______/
+ *         :   :   :
+ */
+static void eepStop (void)
+{
+    out8(I2C_BUS_DAT, 0x00);      /* SCLK = low   SDIO = low */
+    out8(I2C_BUS_DIR, 0x60);      /* set output direction for SCLK/SDIO */
+    udelay(10);
+    out8(I2C_BUS_DAT, 0x40);      /* SCLK = high  SDIO = low */
+    udelay(10);
+    out8(I2C_BUS_DAT, 0x60);      /* SCLK = high  SDIO = high */
+    udelay(10);
+    out8(I2C_BUS_DIR, 0x00);      /* reset to input direction */
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ *  Read one byte from EEPROM
+ *            ___     ___     ___     ___     ___     ___     ___     ___
+ *  SCLK  ___/   \___/   \___/   \___/   \___/   \___/   \___/   \___/   \
+ *        _________________________________________________________________
+ *  SDIO  >     ^       ^       ^       ^       ^       ^       ^       ^
+ *        :  :   :   :   :   :   :   :   :   :   :   :   :   :   :   :   :
+ */
+static unsigned char eepReadByte (void)
+{
+    register unsigned char buf = 0x00;
+    register int i;
+
+    out8(I2C_BUS_DIR, 0x40);
+
+    for (i = 0; i < 8; i++)
+    {
+	out8(I2C_BUS_DAT, 0x00);    /* SCLK = low   SDIO = high */
+	udelay(10);
+	out8(I2C_BUS_DAT, 0x40);    /* SCLK = high  SDIO = high */
+	udelay(15);
+	buf <<= 1;
+	buf = (in8(I2C_BUS_DAT) & 0x20) ? (buf | 0x01) : (buf & 0xFE);
+	out8(I2C_BUS_DAT, 0x00);    /* SCLK = low   SDIO = high */
+	udelay(10);
+    }
+    return(buf);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ *  Write one byte to EEPROM
+ *           ___     ___     ___     ___     ___     ___     ___     ___
+ *  SCLK  __/   \___/   \___/   \___/   \___/   \___/   \___/   \___/   \__
+ *         _______ _______ _______ _______ _______ _______ _______ ________
+ *  SDIO  X_______X_______X_______X_______X_______X_______X_______X________
+ *      :   7   :   6   :   5   :   4   :   3   :   2   :   1   :   0
+ */
+static void eepWriteByte (register unsigned char buf)
+{
+    register int    i;
+
+    (buf & 0x80) ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00);     /* SCLK = low   SDIO = data */
+    out8(I2C_BUS_DIR, 0x60);
+
+    for (i = 7; i >= 0; i--)
+    {
+	(buf & 0x80) ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK=low  SDIO=data */
+	udelay(10);
+	(buf & 0x80) ? out8(I2C_BUS_DAT, 0x60) : out8(I2C_BUS_DAT, 0x40); /* SCLK=high SDIO=data */
+	udelay(15);
+	(buf & 0x80) ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK=low  SDIO=data */
+	udelay(10);
+	buf <<= 1;
+    }
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ *  Read data acknowledge of EEPROM
+ *             _______
+ *  SCLK  ____/       \___
+ *         _______________
+ *  SDIO  >
+ *        :   :   ^   :
+ */
+static int eepReadAck (void)
+{
+    int retval;
+
+    out8(I2C_BUS_DIR, 0x40);
+    out8(I2C_BUS_DAT, 0x00);            /* SCLK = low   SDIO = high */
+    udelay(10);
+    out8(I2C_BUS_DAT, 0x40);            /* SCLK = high  SDIO = high */
+    udelay(10);
+    retval = (in8(I2C_BUS_DAT) & 0x20) ? ERROR : 0;
+    udelay(10);
+    out8(I2C_BUS_DAT, 0x00);            /* SCLK = low   SDIO = high */
+    udelay(10);
+
+    return(retval);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ *  Write data acknowledge to EEPROM
+ *             _______
+ *  SCLK  ____/       \___
+ *
+ *  SDIO  >_______________
+ *        :   :       :
+ */
+static void eepWriteAck (unsigned char ack)
+{
+    ack ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK = low   SDIO = ack */
+    out8(I2C_BUS_DIR, 0x60);
+    udelay(10);
+    ack ? out8(I2C_BUS_DAT, 0x60) : out8(I2C_BUS_DAT, 0x40); /* SCLK = high  SDIO = ack */
+    udelay(15);
+    ack ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK = low   SDIO = ack */
+    udelay(10);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * Read bytes from EEPROM
+ */
+int el_srom_load (addr, buf, cnt, device, block)
+unsigned char addr;
+unsigned char *buf;
+int cnt;
+unsigned char device;
+unsigned char block;
+{
+    register int i;
+
+    for (i=0;i<cnt;i++)
+    {
+	eepStart();
+	eepWriteByte(0xA0 | device | block);
+	if (eepReadAck() == ERROR)
+	{
+	   eepStop();
+	    return(ERROR);
+	}
+	eepWriteByte(addr++);
+	if (eepReadAck() == ERROR)
+	{
+	    eepStop();
+	    return(ERROR);
+	}
+	eepStart();
+
+	eepWriteByte(0xA1 | device | block);
+	if (eepReadAck() == ERROR)
+	{
+	    eepStop();
+	    return(ERROR);
+	}
+
+	*buf++ = eepReadByte();
+	eepWriteAck(1);
+	eepStop();
+
+	if ((addr == 0) && (i != (cnt-1)))    /* is it the same block ? */
+	{
+	    if (block == FIRST_BLOCK)
+		block = SECOND_BLOCK;
+	    else
+		return(ERROR);
+	}
+    }
+    return(cnt);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ *
+ * Write bytes to EEPROM
+ *
+ */
+int el_srom_store (addr, buf, cnt, device, block)
+unsigned char    addr, *buf, device, block;
+int        cnt;
+{
+    register int i, retVal;
+
+    for (i=0;i<cnt;i++)
+    {
+	retVal = ERROR;
+	do
+	{
+	    eepStart();
+	    eepWriteByte(0xA0 | device | block);
+	    if ((retVal = eepReadAck()) == ERROR)
+		eepStop();
+	} while (retVal == ERROR);
+
+	eepWriteByte(addr++);
+	if (eepReadAck() == ERROR)  return(ERROR);
+
+	if ((addr == 0) && (i != (cnt-1)))    /* is it the same block ? */
+	{
+	    if (block == FIRST_BLOCK)
+		block = SECOND_BLOCK;
+	    else
+	    return(ERROR);
+	}
+
+	eepWriteByte(*buf++);
+	if (eepReadAck() == ERROR)
+	    return(ERROR);
+
+	eepStop();
+    }
+    return(cnt);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * calculate checksum for ELTEC revision srom
+ */
+unsigned long el_srom_checksum (ptr, size)
+register unsigned char *ptr;
+unsigned long size;
+{
+    u_long f, accu = 0;
+    u_int  i;
+    u_char byte;
+
+    for (; size; size--)
+    {
+	byte = *ptr++;
+	for (i = 8; i; i--)
+	{
+	    f =  ((byte & 1) ^ (accu & 1)) ? 0x84083001 : 0;
+	    accu >>= 1; accu ^= f;
+	    byte >>= 1;
+	}
+    }
+    return(accu);
+}
+
+/*----------------------------------------------------------------------------*/
diff --git a/board/eltec/bab7xx/flash.c b/board/eltec/bab7xx/flash.c
new file mode 100755
index 0000000..442dd00
--- /dev/null
+++ b/board/eltec/bab7xx/flash.c
@@ -0,0 +1,512 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * 07-10-2002 Frank Gottschling: added 29F032 flash (ELPPC).
+ *        fixed monitor protection part
+ *
+ * 09-18-2001 Andreas Heppel: Reduced the code in here to the usage
+ *        of AMD's 29F040 and 29F016 flashes, since the BAB7xx does use
+ *        any other.
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/pci_io.h>
+
+flash_info_t    flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*flash command address offsets*/
+
+#define ADDR0           (0x555)
+#define ADDR1           (0x2AA)
+#define ADDR3           (0x001)
+
+#define FLASH_WORD_SIZE unsigned char
+
+/*----------------------------------------------------------------------------*/
+
+unsigned long flash_init (void)
+{
+    unsigned long size1, size2;
+    int i;
+
+    /* Init: no FLASHes known */
+    for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
+    {
+	flash_info[i].flash_id = FLASH_UNKNOWN;
+    }
+
+    /* initialise 1st flash */
+    size1 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+    if (flash_info[0].flash_id == FLASH_UNKNOWN)
+    {
+	printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+	    size1, size1<<20);
+    }
+
+    /* initialise 2nd flash */
+    size2 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+    if (flash_info[1].flash_id == FLASH_UNKNOWN)
+    {
+	printf ("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
+	    size2, size2<<20);
+    }
+
+    /* monitor protection ON by default */
+    if (size1 == 512*1024)
+    {
+	(void)flash_protect(FLAG_PROTECT_SET,
+		FLASH_BASE0_PRELIM,
+		FLASH_BASE0_PRELIM+monitor_flash_len-1,
+		&flash_info[0]);
+    }
+    if (size2 == 512*1024)
+    {
+	(void)flash_protect(FLAG_PROTECT_SET,
+		FLASH_BASE1_PRELIM,
+		FLASH_BASE1_PRELIM+monitor_flash_len-1,
+		&flash_info[1]);
+    }
+    if (size2 == 4*1024*1024)
+    {
+	(void)flash_protect(FLAG_PROTECT_SET,
+		CFG_FLASH_BASE,
+		CFG_FLASH_BASE+monitor_flash_len-1,
+		&flash_info[1]);
+    }
+
+    return (size1 + size2);
+}
+
+/*----------------------------------------------------------------------------*/
+
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+    int k;
+    int size;
+    int erased;
+    volatile unsigned long *flash;
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("missing or unknown FLASH type\n");
+	flash_init();
+    }
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("missing or unknown FLASH type\n");
+	return;
+    }
+
+    switch (info->flash_id & FLASH_VENDMASK) {
+    case FLASH_MAN_AMD:
+	printf ("AMD ");
+	break;
+    default:
+	printf ("Unknown Vendor ");
+	break;
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+    case AMD_ID_F040B:
+	printf ("AM29F040B (4 Mbit)\n");
+	break;
+    case AMD_ID_F016D:
+	printf ("AM29F016D (16 Mbit)\n");
+	break;
+    case AMD_ID_F032B:
+	printf ("AM29F032B (32 Mbit)\n");
+	break;
+   default:
+	printf ("Unknown Chip Type\n");
+	break;
+    }
+
+    if (info->size >= (1 << 20)) {
+	printf ("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
+    } else {
+	printf ("  Size: %ld kB in %d Sectors\n", info->size >> 10, info->sector_count);
+    }
+
+    printf ("  Sector Start Addresses:");
+    for (i=0; i<info->sector_count; ++i) {
+	/*
+	* Check if whole sector is erased
+	*/
+	if (i != (info->sector_count-1))
+	    size = info->start[i+1] - info->start[i];
+	else
+	    size = info->start[0] + info->size - info->start[i];
+
+	erased = 1;
+	flash = (volatile unsigned long *)info->start[i];
+	size = size >> 2;        /* divide by 4 for longword access */
+	for (k=0; k<size; k++) {
+	    if (*flash++ != 0xffffffff) {
+		erased = 0;
+		break;
+	    }
+	}
+
+	if ((i % 5) == 0)
+	    printf ("\n   ");
+
+	printf (" %08lX%s%s",
+	    info->start[i],
+	    erased ? " E" : "  ",
+	    info->protect[i] ? "RO " : "   ");
+    }
+    printf ("\n");
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+    short i;
+    ulong vendor, devid;
+    ulong base = (ulong)addr;
+    volatile unsigned char *caddr = (unsigned char *)addr;
+
+#ifdef DEBUG
+    printf("flash_get_size for address 0x%lx: \n", (unsigned long)caddr);
+#endif
+
+    /* Write auto select command: read Manufacturer ID */
+    caddr[0] = 0xF0;   /* reset bank */
+    udelay(10);
+
+    eieio();
+    caddr[0x555] = 0xAA;
+    udelay(10);
+    caddr[0x2AA] = 0x55;
+    udelay(10);
+    caddr[0x555] = 0x90;
+
+    udelay(10);
+
+    vendor = caddr[0];
+    devid = caddr[1];
+
+#ifdef DEBUG
+    printf("Manufacturer: 0x%lx\n", vendor);
+#endif
+
+    vendor &= 0xff;
+    devid &= 0xff;
+
+    /* We accept only two AMD types */
+    switch (vendor) {
+    case (FLASH_WORD_SIZE)AMD_MANUFACT:
+	info->flash_id = FLASH_MAN_AMD;
+	break;
+    default:
+	info->flash_id = FLASH_UNKNOWN;
+	info->sector_count = 0;
+	info->size = 0;
+	return (0);         /* no or unknown flash  */
+    }
+
+    switch (devid) {
+    case (FLASH_WORD_SIZE)AMD_ID_F040B:
+	info->flash_id |= AMD_ID_F040B;
+	info->sector_count = 8;
+	info->size = 0x00080000;
+	break;              /* => 0.5 MB      */
+
+    case (FLASH_WORD_SIZE)AMD_ID_F016D:
+	info->flash_id |= AMD_ID_F016D;
+	info->sector_count = 32;
+	info->size         = 0x00200000;
+	break;              /* => 2 MB      */
+
+    case (FLASH_WORD_SIZE)AMD_ID_F032B:
+	info->flash_id |= AMD_ID_F032B;
+	info->sector_count = 64;
+	info->size         = 0x00400000;
+	break;              /* => 4 MB      */
+
+    default:
+	info->flash_id = FLASH_UNKNOWN;
+	return (0);         /* => no or unknown flash */
+
+    }
+
+#ifdef DEBUG
+    printf("flash id 0x%lx; sector count 0x%x, size 0x%lx\n", info->flash_id, info->sector_count, info->size);
+#endif
+
+    /* check for protected sectors */
+    for (i = 0; i < info->sector_count; i++) {
+	/* sector base address */
+	info->start[i] = base + i * (info->size / info->sector_count);
+	/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+	/* D0 = 1 if protected */
+	caddr = (volatile unsigned char *)(info->start[i]);
+	info->protect[i] = caddr[2] & 1;
+    }
+
+    /*
+     * Prevent writes to uninitialized FLASH.
+     */
+    if (info->flash_id != FLASH_UNKNOWN) {
+	caddr = (volatile unsigned char *)info->start[0];
+	caddr[0] = 0xF0;   /* reset bank */
+    }
+
+    return (info->size);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+    int flag, prot, sect, l_sect;
+    ulong start, now, last;
+    int rc = 0;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+	if (info->flash_id == FLASH_UNKNOWN) {
+	    printf ("- missing\n");
+	} else {
+	    printf ("- no sectors to erase\n");
+	}
+	return 1;
+    }
+
+    if ((info->flash_id == FLASH_UNKNOWN) ||
+	(info->flash_id > FLASH_AMD_COMP)) {
+	printf ("Can't erase unknown flash type - aborted\n");
+	return 1;
+    }
+
+    prot = 0;
+    for (sect=s_first; sect<=s_last; ++sect) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+
+    if (prot) {
+	printf ("- Warning: %d protected sectors will not be erased!\n",
+	    prot);
+    } else {
+	printf ("\n");
+    }
+
+    l_sect = -1;
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+    addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+    addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+    addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+    addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect<=s_last; sect++) {
+	if (info->protect[sect] == 0) { /* not protected */
+	    addr = (FLASH_WORD_SIZE *)(info->start[sect]);
+	    if (info->flash_id & FLASH_MAN_SST) {
+		addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+		addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+		addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+		addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+		addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+		addr[0] = (FLASH_WORD_SIZE)0x00500050;  /* block erase */
+		udelay(30000);  /* wait 30 ms */
+	    }
+	    else
+		addr[0] = (FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+	    l_sect = sect;
+	}
+    }
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+	enable_interrupts();
+
+    /* wait at least 80us - let's wait 1 ms */
+    udelay (1000);
+
+    /*
+     * We wait for the last triggered sector
+     */
+    if (l_sect < 0)
+	goto DONE;
+
+    start = get_timer (0);
+    last  = start;
+    addr = (FLASH_WORD_SIZE *)(info->start[l_sect]);
+    while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+	if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	    printf ("Timeout\n");
+	    return 1;
+	}
+	/* show that we're waiting */
+	if ((now - last) > 1000) {  /* every second */
+	    serial_putc ('.');
+	    last = now;
+	}
+    }
+
+DONE:
+    /* reset to read mode */
+    addr = (FLASH_WORD_SIZE *)info->start[0];
+    addr[0] = (FLASH_WORD_SIZE)0x00F000F0;  /* reset bank */
+
+    printf (" done\n");
+    return rc;
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp, data;
+    int i, l, rc;
+
+    wp = (addr & ~3);   /* get lower word aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i=0, cp=wp; i<l; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+	for (; i<4 && cnt>0; ++i) {
+	    data = (data << 8) | *src++;
+	    --cnt;
+	    ++cp;
+	}
+	for (; cnt==0 && i<4; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp += 4;
+    }
+
+    /*
+     * handle word aligned part
+     */
+    while (cnt >= 4) {
+	data = 0;
+	for (i=0; i<4; ++i) {
+	    data = (data << 8) | *src++;
+	}
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp  += 4;
+	cnt -= 4;
+    }
+
+    if (cnt == 0) {
+	return (0);
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+	data = (data << 8) | *src++;
+	--cnt;
+    }
+    for (; i<4; ++i, ++cp) {
+	data = (data << 8) | (*(uchar *)cp);
+    }
+
+    return (write_word(info, wp, data));
+}
+
+/*----------------------------------------------------------------------------*/
+/* Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
+    ulong start;
+    int flag;
+	int i;
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*((volatile FLASH_WORD_SIZE *)dest) &
+	     (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
+	return (2);
+    }
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+	for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
+	  {
+	    addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+	    addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+	    addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0;
+
+	    dest2[i] = data2[i];
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+	      enable_interrupts();
+
+	    /* data polling for D7 */
+	    start = get_timer (0);
+	    while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
+		   (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
+	      if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		return (1);
+	      }
+	    }
+	  }
+
+    return (0);
+}
+
+/*----------------------------------------------------------------------------*/
diff --git a/board/eltec/bab7xx/l2cache.c b/board/eltec/bab7xx/l2cache.c
new file mode 100755
index 0000000..1e75377
--- /dev/null
+++ b/board/eltec/bab7xx/l2cache.c
@@ -0,0 +1,159 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CFG_L2_BAB7xx)
+
+#include <pci.h>
+#include <mpc106.h>
+#include <asm/processor.h>
+
+/* defines L2CR register for MPC750 */
+
+#define L2CR_E           0x80000000
+#define L2CR_256K        0x10000000
+#define L2CR_512K        0x20000000
+#define L2CR_1024K       0x30000000
+#define L2CR_I           0x00200000
+#define L2CR_SL          0x00008000
+#define L2CR_IP          0x00000001
+
+/*----------------------------------------------------------------------------*/
+
+static int dummy (int dummy)
+{
+    return (dummy+1);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int l2_cache_enable (int l2control)
+{
+    if (l2control)              /* BAB750 */
+    {
+	mtspr(SPRN_L2CR, l2control);
+	mtspr(SPRN_L2CR, (l2control | L2CR_I));
+	while (mfspr(SPRN_L2CR) & L2CR_IP)
+	    ;
+	mtspr(SPRN_L2CR, (l2control | L2CR_E));
+	return (0);
+    }
+    else /* BAB740 */
+    {
+	int picr1, picr2, mask;
+	int picr2CacheSize, cacheSize;
+	int *d;
+	int devbusfn;
+	u32 reg32;
+
+	devbusfn = pci_find_device(PCI_VENDOR_ID_MOTOROLA,
+				   PCI_DEVICE_ID_MOTOROLA_MPC106, 0);
+	if (devbusfn == -1)
+	    return (-1);
+
+	pci_read_config_dword  (devbusfn, PCI_PICR2, &reg32);
+	reg32 &= ~PICR2_L2_EN;
+	pci_write_config_dword (devbusfn, PCI_PICR2, reg32);
+
+	/* cache size */
+	if (*(volatile unsigned char *) (CFG_ISA_IO + 0x220) & 0x04)
+	{
+	    /* cache size is 512 KB */
+	    picr2CacheSize = PICR2_L2_SIZE_512K;
+	    cacheSize = 0x80000;
+	}
+	else
+	{
+	    /* cache size is 256 KB */
+	    picr2CacheSize = PICR2_L2_SIZE_256K;
+	    cacheSize = 0x40000;
+	}
+
+	/* setup PICR1 */
+	mask =
+	~(PICR1_CF_BREAD_WS(1) |
+	  PICR1_CF_BREAD_WS(2) |
+	  PICR1_CF_CBA(0xff) |
+	  PICR1_CF_CACHE_1G |
+	  PICR1_CF_DPARK |
+	  PICR1_CF_APARK |
+	  PICR1_CF_L2_CACHE_MASK);
+
+	picr1 =
+	(PICR1_CF_CBA(0x3f) |
+	 PICR1_CF_CACHE_1G |
+	 PICR1_CF_APARK |
+	 PICR1_CF_DPARK |
+	 PICR1_CF_L2_COPY_BACK); /* PICR1_CF_L2_WRITE_THROUGH */
+
+	pci_read_config_dword  (devbusfn, PCI_PICR1, &reg32);
+	reg32 &= mask;
+	reg32 |= picr1;
+	pci_write_config_dword (devbusfn, PCI_PICR1, reg32);
+
+	/*
+	 * invalidate all L2 cache
+	 */
+	picr2 =
+	(PICR2_CF_INV_MODE |
+	 PICR2_CF_HIT_HIGH |
+	 PICR2_CF_MOD_HIGH |
+	 PICR2_CF_L2_HIT_DELAY(1) |
+	 PICR2_CF_APHASE_WS(1) |
+	 picr2CacheSize);
+
+	pci_write_config_dword (devbusfn, PCI_PICR2, picr2);
+
+	/*
+	 * dummy transactions
+	 */
+	for (d=0; d<(int *)(2*cacheSize); d++)
+	    dummy(*d);
+
+	pci_write_config_dword (devbusfn, PCI_PICR2,
+				(picr2 | PICR2_CF_FLUSH_L2));
+
+	/* setup PICR2 */
+	picr2 =
+	(PICR2_CF_FAST_CASTOUT |
+	 PICR2_CF_WDATA |
+	 PICR2_CF_ADDR_ONLY_DISABLE |
+	 PICR2_CF_HIT_HIGH |
+	 PICR2_CF_MOD_HIGH |
+	 PICR2_L2_UPDATE_EN |
+	 PICR2_L2_EN |
+	 PICR2_CF_APHASE_WS(1) |
+	 PICR2_CF_DATA_RAM_PBURST |
+	 PICR2_CF_L2_HIT_DELAY(1) |
+	 PICR2_CF_SNOOP_WS(2) |
+	 picr2CacheSize);
+
+	pci_write_config_dword (devbusfn, PCI_PICR2, picr2);
+    }
+    return (0);
+}
+
+/*----------------------------------------------------------------------------*/
+
+#endif /* (CFG_L2_BAB7xx) */
diff --git a/board/eltec/bab7xx/misc.c b/board/eltec/bab7xx/misc.c
new file mode 100755
index 0000000..6a24807
--- /dev/null
+++ b/board/eltec/bab7xx/misc.c
@@ -0,0 +1,547 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* includes */
+#include <common.h>
+#include <linux/ctype.h>
+#include <pci.h>
+#include <net.h>
+#include <mpc106.h>
+#include <w83c553f.h>
+#include "srom.h"
+
+/* imports  */
+extern char console_buffer[CFG_CBSIZE];
+extern int l2_cache_enable (int l2control);
+extern void *nvram_read (void *dest, const short src, size_t count);
+extern void nvram_write (short dest, const void *src, size_t count);
+
+/* globals */
+unsigned int ata_reset_time = 60;
+unsigned int scsi_reset_time = 10;
+unsigned int eltec_board;
+
+/* BAB750 uses SYM53C875(default) and BAB740 uses SYM53C860
+ * values fixed after board identification
+ */
+unsigned short scsi_dev_id = PCI_DEVICE_ID_NCR_53C875;
+unsigned int   scsi_max_scsi_id = 15;
+unsigned char  scsi_sym53c8xx_ccf = 0x13;
+
+/*----------------------------------------------------------------------------*/
+/*
+ * handle sroms on BAB740/750
+ * fix ether address
+ * L2 cache initialization
+ * ide dma control
+ */
+int misc_init_r (void)
+{
+    revinfo eerev;
+    char *ptr;
+    u_int  i, l, initSrom, copyNv;
+    char buf[256];
+    char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
+	     0, 0, 0, 0, 10, 11, 12, 13, 14, 15 };
+    pci_dev_t bdf;
+
+    char sromSYM[] = {
+#ifdef TULIP_BUG
+    /* 10BaseT, 100BaseTx no full duplex modes */
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x08,
+    0x02, 0x86, 0x02, 0x00, 0xaf, 0x08, 0xa5, 0x00,
+    0x88, 0x04, 0x03, 0x27, 0x08, 0x25, 0x00, 0x61,
+    0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc6, 0xe8
+#endif
+    /* 10BaseT, 10BaseT-FD, 100BaseTx, 100BaseTx-FD */
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x08,
+    0x04, 0x86, 0x02, 0x00, 0xaf, 0x08, 0xa5, 0x00,
+    0x86, 0x02, 0x04, 0xaf, 0x08, 0xa5, 0x00, 0x88,
+    0x04, 0x03, 0x27, 0x08, 0x25, 0x00, 0x61, 0x80,
+    0x88, 0x04, 0x05, 0x27, 0x08, 0x25, 0x00, 0x61,
+    0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x77
+    };
+
+    char sromMII[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x5b, 0x00,
+    0x2e, 0x4d, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x08,
+    0x01, 0x95, 0x03, 0x00, 0x00, 0x04, 0x01, 0x08,
+    0x00, 0x00, 0x02, 0x08, 0x02, 0x00, 0x00, 0x78,
+    0xe0, 0x01, 0x00, 0x50, 0x00, 0x18, 0x80, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xde, 0x41
+    };
+
+    /*
+     * Check/Remake revision info
+     */
+    initSrom = 0;
+    copyNv   = 0;
+
+    /* read out current revision srom contens */
+    el_srom_load (0x0000, (u_char*)&eerev, sizeof(revinfo),
+		SECOND_DEVICE, FIRST_BLOCK);
+
+    /* read out current nvram shadow image */
+    nvram_read (buf, CFG_NV_SROM_COPY_ADDR, CFG_SROM_SIZE);
+
+    if (strcmp (eerev.magic, "ELTEC") != 0)
+    {
+	/* srom is not initialized -> create a default revision info */
+	for (i = 0, ptr = (char *)&eerev; i < sizeof(revinfo); i++)
+	    *ptr++ = 0x00;
+	strcpy(eerev.magic, "ELTEC");
+	eerev.revrev[0] = 1;
+	eerev.revrev[1] = 0;
+	eerev.size = 0x00E0;
+	eerev.category[0] = 0x01;
+
+	/* node id from dead e128 as default */
+	eerev.etheraddr[0] = 0x00;
+	eerev.etheraddr[1] = 0x00;
+	eerev.etheraddr[2] = 0x5B;
+	eerev.etheraddr[3] = 0x00;
+	eerev.etheraddr[4] = 0x2E;
+	eerev.etheraddr[5] = 0x4D;
+
+	/* cache config word for bab750 */
+	*(int*)&eerev.res[0] = CLK2P0TO1_1MB_PB_0P5DH;
+
+	initSrom = 1;  /* force dialog */
+	copyNv   = 1;  /* copy to nvram */
+    }
+
+    if ((copyNv == 0) &&   (el_srom_checksum((u_char*)&eerev, CFG_SROM_SIZE) !=
+		el_srom_checksum((u_char*)buf, CFG_SROM_SIZE)))
+    {
+	printf ("Invalid revision info copy in nvram !\n");
+	printf ("Press key:\n  <c> to copy current revision info to nvram.\n");
+	printf ("  <r> to reenter revision info.\n");
+	printf ("=> ");
+	if (0 != readline (NULL))
+	{
+	    switch ((char)toupper(console_buffer[0]))
+	    {
+	    case 'C':
+		copyNv = 1;
+		break;
+	    case 'R':
+		copyNv = 1;
+		initSrom = 1;
+		break;
+	    }
+	}
+    }
+
+    if (initSrom)
+    {
+	memcpy (buf, &eerev.revision[0][0], 14);     /* save all revision info */
+	printf ("Enter revision number (0-9): %c  ", eerev.revision[0][0]);
+	if (0 != readline (NULL))
+	{
+	    eerev.revision[0][0] = (char)toupper(console_buffer[0]);
+	    memcpy (&eerev.revision[1][0], buf, 12); /* shift rest of rev info */
+	}
+
+	printf ("Enter revision character (A-Z): %c  ", eerev.revision[0][1]);
+	if (1 == readline (NULL))
+	{
+	    eerev.revision[0][1] = (char)toupper(console_buffer[0]);
+	}
+
+	printf ("Enter board name (V-XXXX-XXXX): %s  ", (char *)&eerev.board);
+	if (11 == readline (NULL))
+	{
+	    for (i=0; i<11; i++)
+		eerev.board[i] =  (char)toupper(console_buffer[i]);
+	    eerev.board[11] = '\0';
+	}
+
+	printf ("Enter serial number: %s ", (char *)&eerev.serial );
+	if (6 == readline (NULL))
+	{
+	    for (i=0; i<6; i++)
+		eerev.serial[i] = console_buffer[i];
+	    eerev.serial[6] = '\0';
+	}
+
+	printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x  ",
+	    eerev.etheraddr[0], eerev.etheraddr[1],
+	    eerev.etheraddr[2], eerev.etheraddr[3],
+	    eerev.etheraddr[4], eerev.etheraddr[5]);
+	if (12 == readline (NULL))
+	{
+	    for (i=0; i<12; i+=2)
+	    eerev.etheraddr[i>>1] = (char)(16*hex[toupper(console_buffer[i])-'0'] +
+			       hex[toupper(console_buffer[i+1])-'0']);
+	}
+
+	l = strlen ((char *)&eerev.text);
+	printf("Add to text section (max 64 chr): %s ", (char *)&eerev.text );
+	if (0 != readline (NULL))
+	{
+	    for (i = l; i<63; i++)
+		eerev.text[i] = console_buffer[i-l];
+	    eerev.text[63] = '\0';
+	}
+
+	if (strstr ((char *)&eerev.board, "75") != NULL)
+	    eltec_board = 750;
+	else
+	    eltec_board = 740;
+
+	if (eltec_board == 750)
+	{
+	    if (CPU_TYPE == CPU_TYPE_750)
+		*(int*)&eerev.res[0] = CLK2P0TO1_1MB_PB_0P5DH;
+		else
+		*(int*)&eerev.res[0] = CLK2P5TO1_1MB_PB_0P5DH;
+
+	    printf("Enter L2Cache config word with leading zero (HEX): %08X  ",
+		    *(int*)&eerev.res[0] );
+	    if (0 != readline (NULL))
+	    {
+		for (i=0; i<7; i+=2)
+		{
+		    eerev.res[i>>1] =
+		    (char)(16*hex[toupper(console_buffer[i])-'0'] +
+		    hex[toupper(console_buffer[i+1])-'0']);
+		}
+	    }
+
+	    /* prepare network eeprom */
+	    sromMII[20] = eerev.etheraddr[0];
+	    sromMII[21] = eerev.etheraddr[1];
+	    sromMII[22] = eerev.etheraddr[2];
+	    sromMII[23] = eerev.etheraddr[3];
+	    sromMII[24] = eerev.etheraddr[4];
+	    sromMII[25] = eerev.etheraddr[5];
+	    printf("\nSRom:  Writing DEC21143 MII info .. ");
+
+	    if (dc_srom_store ((u_short *)sromMII) == -1)
+		printf("FAILED\n");
+	    else
+		printf("OK\n");
+	}
+
+	if (eltec_board == 740)
+	{
+	    *(int *)&eerev.res[0] = 0;
+	    sromSYM[20] = eerev.etheraddr[0];
+	    sromSYM[21] = eerev.etheraddr[1];
+	    sromSYM[22] = eerev.etheraddr[2];
+	    sromSYM[23] = eerev.etheraddr[3];
+	    sromSYM[24] = eerev.etheraddr[4];
+	    sromSYM[25] = eerev.etheraddr[5];
+	    printf("\nSRom:  Writing DEC21143 SYM info .. ");
+
+	    if (dc_srom_store ((u_short *)sromSYM) == -1)
+		printf("FAILED\n");
+	    else
+		printf("OK\n");
+	}
+
+	/* update CRC */
+	eerev.crc = el_srom_checksum((u_char *)eerev.board, eerev.size);
+
+	/* write new values */
+	printf("\nSRom:  Writing revision info ...... ");
+	if (el_srom_store((BLOCK_SIZE-sizeof(revinfo)), (u_char *)&eerev,
+			    sizeof(revinfo), SECOND_DEVICE, FIRST_BLOCK) == -1)
+	    printf("FAILED\n\n");
+	else
+	    printf("OK\n\n");
+
+	/* write new values as shadow image to nvram */
+	nvram_write (CFG_NV_SROM_COPY_ADDR, (void *)&eerev, CFG_SROM_SIZE);
+
+    } /*if (initSrom) */
+
+    /* copy current values as shadow image to nvram */
+    if (initSrom == 0 && copyNv == 1)
+	nvram_write (CFG_NV_SROM_COPY_ADDR, (void *)&eerev, CFG_SROM_SIZE);
+
+    /* update environment */
+    sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
+	    eerev.etheraddr[0], eerev.etheraddr[1],
+	    eerev.etheraddr[2], eerev.etheraddr[3],
+	    eerev.etheraddr[4], eerev.etheraddr[5]);
+    setenv ("ethaddr", buf);
+
+    /* print actual board identification */
+    printf("Ident: %s  Ser %s  Rev %c%c\n",
+	    eerev.board, (char *)&eerev.serial,
+	    eerev.revision[0][0], eerev.revision[0][1]);
+
+    /* global board ident */
+    if (strstr ((char *)&eerev.board, "75") != NULL)
+	eltec_board = 750;
+    else
+	eltec_board = 740;
+
+   /*
+    * L2 cache configuration
+    */
+#if defined(CFG_L2_BAB7xx)
+    ptr = getenv("l2cache");
+    if (*ptr == '0')
+    {
+	printf ("Cache: L2 NOT activated on BAB%d\n", eltec_board);
+    }
+    else
+    {
+	printf ("Cache: L2 activated on BAB%d\n", eltec_board);
+	l2_cache_enable(*(int*)&eerev.res[0]);
+    }
+#endif
+
+   /*
+    * Reconfig ata reset timeout from environment
+    */
+    if ((ptr = getenv ("ata_reset_time")) != NULL)
+    {
+	ata_reset_time = (int)simple_strtoul (ptr, NULL, 10);
+    }
+    else
+    {
+	sprintf (buf, "%d", ata_reset_time);
+	setenv ("ata_reset_time", buf);
+    }
+
+   /*
+    * Reconfig scsi reset timeout from environment
+    */
+    if ((ptr = getenv ("scsi_reset_time")) != NULL)
+    {
+	scsi_reset_time = (int)simple_strtoul (ptr, NULL, 10);
+    }
+    else
+    {
+	sprintf (buf, "%d", scsi_reset_time);
+	setenv ("scsi_reset_time", buf);
+    }
+
+
+    if ((bdf = pci_find_device(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, 0)) > 0)
+    {
+	if (pci_find_device(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C860, 0) > 0)
+	{
+	    /* BAB740 with SCSI=IRQ 11; SCC=IRQ 9; no IDE; NCR860 at 80 Mhz */
+	    scsi_dev_id = PCI_DEVICE_ID_NCR_53C860;
+	    scsi_max_scsi_id = 7;
+	    scsi_sym53c8xx_ccf = 0x15;
+	    pci_write_config_byte (bdf, WINBOND_IDEIRCR, 0xb0);
+	}
+
+	if ((ptr = getenv ("ide_dma_off")) != NULL)
+	{
+	    u_long dma_off = simple_strtoul (ptr, NULL, 10);
+	    /*
+	    * setup user defined registers
+	    * s.a. linux/drivers/ide/sl82c105.c
+	    */
+	    bdf |= PCI_BDF(0,0,1);            /* ide user reg at bdf function 1 */
+	    if (dma_off & 1)
+	    {
+		pci_write_config_byte (bdf, 0x46, 1);
+		printf("IDE:   DMA off flag set: Bus 0 : Dev 0\n");
+	    }
+	    if (dma_off & 2)
+	    {
+		pci_write_config_byte (bdf, 0x4a, 1);
+		printf("IDE:   DMA off flag set: Bus 0 : Dev 1\n");
+	    }
+	    if (dma_off & 4)
+	    {
+		pci_write_config_byte (bdf, 0x4e, 1);
+		printf("IDE:   DMA off flag set: Bus 1 : Dev 0\n");
+	    }
+	    if (dma_off & 8)
+	    {
+		pci_write_config_byte (bdf, 0x52, 1);
+		printf("IDE:   DMA off flag set: Bus 1 : Dev 1\n");
+	    }
+	}
+    }
+    return (0);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * BAB740 uses KENDIN KS8761 modem chip with not common setup values
+ */
+#ifdef CONFIG_TULIP_SELECT_MEDIA
+
+/* Register bits.
+ */
+#define BMR_SWR         0x00000001      /* Software Reset */
+#define STS_TS          0x00700000      /* Transmit Process State */
+#define STS_RS          0x000e0000      /* Receive Process State */
+#define OMR_ST          0x00002000      /* Start/Stop Transmission Command */
+#define OMR_SR          0x00000002      /* Start/Stop Receive */
+#define OMR_PS          0x00040000      /* Port Select */
+#define OMR_SDP         0x02000000      /* SD Polarity - MUST BE ASSERTED */
+#define OMR_PM          0x00000080      /* Pass All Multicast */
+#define OMR_PR          0x00000040      /* Promiscuous Mode */
+#define OMR_PCS         0x00800000      /* PCS Function */
+#define OMR_TTM         0x00400000      /* Transmit Threshold Mode */
+
+/* Ethernet chip registers.
+ */
+#define DE4X5_BMR       0x000           /* Bus Mode Register */
+#define DE4X5_TPD       0x008           /* Transmit Poll Demand Reg */
+#define DE4X5_RRBA      0x018           /* RX Ring Base Address Reg */
+#define DE4X5_TRBA      0x020           /* TX Ring Base Address Reg */
+#define DE4X5_STS       0x028           /* Status Register */
+#define DE4X5_OMR       0x030           /* Operation Mode Register */
+#define DE4X5_SISR      0x060           /* SIA Status Register */
+#define DE4X5_SICR      0x068           /* SIA Connectivity Register */
+#define DE4X5_TXRX      0x070           /* SIA Transmit and Receive Register */
+#define DE4X5_GPPR      0x078           /* General Purpose Port register */
+#define DE4X5_APROM      0x048          /* Ethernet Address PROM */
+
+/*----------------------------------------------------------------------------*/
+
+static int INL(struct eth_device* dev, u_long addr)
+{
+    return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase));
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void OUTL(struct eth_device* dev, int command, u_long addr)
+{
+    *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command);
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void media_reg_init (
+    struct eth_device* dev,
+    u32 csr14,
+    u32 csr15_dir,
+    u32 csr15_v0,
+    u32 csr15_v1,
+    u32 csr6 )
+{
+    OUTL(dev, 0, DE4X5_OMR);            /* CSR6  */
+    udelay(10 * 1000);
+    OUTL(dev, 0, DE4X5_SICR);           /* CSR13 */
+    OUTL(dev, 1, DE4X5_SICR);           /* CSR13 */
+    udelay(10 * 1000);
+    OUTL(dev, csr14, DE4X5_TXRX);       /* CSR14 */
+    OUTL(dev, csr15_dir, DE4X5_GPPR);   /* CSR15 */
+    OUTL(dev, csr15_v0,  DE4X5_GPPR);   /* CSR15 */
+    udelay(10 * 1000);
+    OUTL(dev, csr15_v1,  DE4X5_GPPR);   /* CSR15 */
+    OUTL(dev, 0x00000301, DE4X5_SISR);  /* CSR12 */
+    OUTL(dev, csr6, DE4X5_OMR);         /* CSR6 */
+}
+
+/*----------------------------------------------------------------------------*/
+
+void dc21x4x_select_media(struct eth_device* dev)
+{
+    int i, status, ext;
+    extern unsigned int eltec_board;
+
+    if (eltec_board == 740)
+    {
+	printf("SYM media select "); /* BAB740 */
+	/* start autoneg. with 10 mbit */
+	media_reg_init (dev, 0x3ffff, 0x08af0008, 0x00a10008, 0x00a50008, 0x02400080);
+	ext = status = 0;
+	for (i=0; i<2000+ext; i++)
+	{
+	    status = INL(dev, DE4X5_SISR);
+	    udelay(1000);
+	    if (status & 0x2000) ext = 2000;
+	    if ((status & 0x7000) == 0x5000) break;
+	}
+
+	/* autoneg. ok -> 100MB FD */
+	if ((status & 0x0100f000) == 0x0100d000)
+	{
+	    media_reg_init (dev, 0x37f7f, 0x08270008, 0x00210008, 0x00250008, 0x03c40280);
+	    printf("100baseTx-FD\n");
+	}
+	/* autoneg. ok -> 100MB HD */
+	else if ((status & 0x0080f000) == 0x0080d000)
+	{
+	    media_reg_init (dev, 0x17f7f, 0x08270008, 0x00210008, 0x00250008, 0x03c40080);
+	    printf("100baseTx\n");
+	}
+	/* autoneg. ok -> 10MB FD */
+	else if ((status & 0x0040f000) == 0x0040d000)
+	{
+	    media_reg_init (dev, 0x07f7f, 0x08af0008, 0x00a10008, 0x00a50008, 0x02400280);
+	    printf("10baseT-FD\n");
+	}
+	/* autoneg. fail -> 10MB HD */
+	else
+	{
+	    media_reg_init (dev, 0x7f7f, 0x08af0008, 0x00a10008, 0x00a50008,
+			(OMR_SDP | OMR_TTM | OMR_PM));
+	    printf("10baseT\n");
+	}
+    }
+    else
+    {
+	printf("MII media selected\n");                     /* BAB750 */
+	OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);    /* CSR6 */
+    }
+}
+#endif /* CONFIG_TULIP_SELECT_MEDIA */
+
+/*---------------------------------------------------------------------------*/
diff --git a/board/eltec/bab7xx/pci.c b/board/eltec/bab7xx/pci.c
new file mode 100755
index 0000000..edbd3dd
--- /dev/null
+++ b/board/eltec/bab7xx/pci.c
@@ -0,0 +1,120 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * PCI initialisation for the MPC10x.
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <mpc106.h>
+
+#ifdef CONFIG_PCI
+
+struct pci_controller local_hose;
+
+void pci_init_board(void)
+{
+    struct pci_controller* hose = (struct pci_controller *)&local_hose;
+    u32 reg32;
+    u16 reg16;
+
+    hose->first_busno = 0;
+    hose->last_busno = 0xff;
+
+    pci_set_region(hose->regions + 0,
+	CFG_PCI_MEMORY_BUS,
+	CFG_PCI_MEMORY_PHYS,
+    /*
+    * Attention: pci_hose_phys_to_bus() failes in address compare,
+    * so we need (CFG_PCI_MEMORY_SIZE-1)
+    */
+	CFG_PCI_MEMORY_SIZE-1,
+	PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+    /* PCI memory space */
+    pci_set_region(hose->regions + 1,
+	CFG_PCI_MEM_BUS,
+	CFG_PCI_MEM_PHYS,
+	CFG_PCI_MEM_SIZE,
+	PCI_REGION_MEM);
+
+    /* ISA/PCI memory space */
+    pci_set_region(hose->regions + 2,
+	CFG_ISA_MEM_BUS,
+	CFG_ISA_MEM_PHYS,
+	CFG_ISA_MEM_SIZE,
+	PCI_REGION_MEM);
+
+    /* PCI I/O space */
+    pci_set_region(hose->regions + 3,
+	CFG_PCI_IO_BUS,
+	CFG_PCI_IO_PHYS,
+	CFG_PCI_IO_SIZE,
+	PCI_REGION_IO);
+
+    /* ISA/PCI I/O space */
+    pci_set_region(hose->regions + 4,
+	CFG_ISA_IO_BUS,
+	CFG_ISA_IO_PHYS,
+	CFG_ISA_IO_SIZE,
+	PCI_REGION_IO);
+
+    hose->region_count = 5;
+
+    pci_setup_indirect(hose,
+	MPC106_REG_ADDR,
+	MPC106_REG_DATA);
+
+    pci_register_hose(hose);
+
+    hose->last_busno = pci_hose_scan(hose);
+
+    /* Initialises the MPC10x PCI Configuration regs. */
+    pci_read_config_dword (PCI_BDF(0,0,0), PCI_PICR2, &reg32);
+    reg32 |= PICR2_CF_SNOOP_WS(3) |
+	     PICR2_CF_FLUSH_L2 |
+	     PICR2_CF_L2_HIT_DELAY(3) |
+	     PICR2_CF_APHASE_WS(3);
+    reg32 &= ~(PICR2_L2_EN | PICR2_L2_UPDATE_EN);
+    pci_write_config_dword (PCI_BDF(0,0,0), PCI_PICR2, reg32);
+
+    pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
+    reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+    pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
+
+    /* Clear non-reserved bits in status register */
+    pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
+
+    pci_read_config_dword (PCI_BDF(0,0,0), PCI_PICR1, &reg32);
+    reg32 |= PICR1_CF_CBA(63) |
+	     PICR1_CF_BREAD_WS(2) |
+	     PICR1_MCP_EN |
+	     PICR1_CF_DPARK |
+	     PICR1_PROC_TYPE_604 |
+	     PICR1_CF_LOOP_SNOOP |
+	     PICR1_CF_APARK;
+    pci_write_config_dword (PCI_BDF(0,0,0), PCI_PICR1, reg32);
+}
+
+#endif /* CONFIG_PCI */
diff --git a/board/eltec/bab7xx/srom.h b/board/eltec/bab7xx/srom.h
new file mode 100755
index 0000000..c18ab91
--- /dev/null
+++ b/board/eltec/bab7xx/srom.h
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* common srom defs */
+#define FIRST_DEVICE            0x00
+#define SECOND_DEVICE           0x04
+#define FIRST_BLOCK             0x00
+#define SECOND_BLOCK            0x02
+#define BLOCK_SIZE              0x100
+#define ERROR                   (-1)
+
+#define CLK2P0TO1_1MB_PB_0P5DH  0x79000100
+#define CLK2P5TO1_1MB_PB_0P5DH  0x7B000100
+
+#define CPU_TYPE_740            0x08
+#define CPU_TYPE_750            0x08
+#define CPU_TYPE                ((get_pvr()>>16)&0xffff)
+
+#define ABS(x)                  ((x<0)?-x:x)
+#define SROM_SHORT(pX)          (*(u8 *)(pX) | *((u8 *)(pX)+1) << 8)
+
+/* bab7xx ELTEC srom */
+#define I2C_BUS_DAT             (CFG_ISA_IO + 0x220)
+#define I2C_BUS_DIR             (CFG_ISA_IO + 0x221)
+
+/* srom at mpc107 */
+#define MPC107_I2CADDR          (mpc107_eumb_addr + 0x3000)     /* address      */
+#define MPC107_I2CFDR           (mpc107_eumb_addr + 0x3004)     /* freq divider */
+#define MPC107_I2CCR            (mpc107_eumb_addr + 0x3008)     /* control      */
+#define MPC107_I2CSR            (mpc107_eumb_addr + 0x300c)     /* status       */
+#define MPC107_I2CDR            (mpc107_eumb_addr + 0x3010)     /* data         */
+#define MPC107_I2C_TIMEOUT      10000000
+
+/* i82559 */
+#define EE_ADDR_BITS            6
+#define EE_SIZE                 0x40                            /* 0x40 words */
+#define EE_CHECKSUM             0xBABA
+
+/* dc21143 */
+#define DEC_SROM_SIZE           128
+
+
+/*
+ * structure of revision srom
+ */
+typedef struct  {
+    char    magic[8];           /* 000 - Magic number */
+    char    revrev[2];          /* 008 - Revision of structure */
+    unsigned short size;        /* 00A - Size of CRC area */
+    unsigned long  crc;         /* 00C - CRC */
+    char    board[16];          /* 010 - Board Revision information */
+    char    option[4][16];      /* 020 - Option Revision information */
+    char    serial[8];          /* 060 - Board serial number */
+    char    etheraddr[6];       /* 068 - Ethernet node addresse */
+    char    reserved[2];        /* 06E - Reserved */
+    char    revision[7][2];     /* 070 - Revision codes */
+    char    category[2];        /* 07E - Category codes */
+    char    text[64];           /* 080 - Text field */
+    char    res[64];            /* 0C0 - Reserved */
+} revinfo;
+
+unsigned long el_srom_checksum (unsigned char *ptr, unsigned long size);
+int el_srom_load  (unsigned char addr, unsigned char *buf, int cnt,
+		   unsigned char device, unsigned char block);
+int el_srom_store (unsigned char addr, unsigned char *buf, int cnt,
+		   unsigned char device, unsigned char block);
+
+int mpc107_i2c_init (unsigned long eumb_addr, unsigned long divider);
+int mpc107_i2c_read_byte (unsigned char device, unsigned char block, unsigned char offset);
+int mpc107_i2c_write_byte (unsigned char device, unsigned char block,
+			   unsigned char offset, unsigned char val);
+int mpc107_srom_load (unsigned char addr, unsigned char *pBuf, int cnt,
+		      unsigned char device, unsigned char block);
+int mpc107_srom_store (unsigned char addr, unsigned char *pBuf, int cnt,
+		       unsigned char device, unsigned char block);
+
+int dc_srom_load (unsigned short *dest);
+int dc_srom_store (unsigned short *src);
+
+unsigned short eepro100_srom_checksum (unsigned short *sromdata);
+void eepro100_srom_load (unsigned short *destination);
+int  eepro100_srom_store (unsigned short *source);
diff --git a/board/eltec/bab7xx/u-boot.lds b/board/eltec/bab7xx/u-boot.lds
new file mode 100755
index 0000000..d89eb6c
--- /dev/null
+++ b/board/eltec/bab7xx/u-boot.lds
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/74xx_7xx/start.o	(.text)
+
+/* store the environment in a seperate sector in the boot flash */
+/*    . = env_offset; */
+/*    common/environment.o(.text) */
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}