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| author | Srikant Patnaik | 2015-01-11 12:28:04 +0530 |
|---|---|---|
| committer | Srikant Patnaik | 2015-01-11 12:28:04 +0530 |
| commit | 871480933a1c28f8a9fed4c4d34d06c439a7a422 (patch) | |
| tree | 8718f573808810c2a1e8cb8fb6ac469093ca2784 /ANDROID_3.4.5/arch/m68k/include/asm/mcfslt.h | |
| parent | 9d40ac5867b9aefe0722bc1f110b965ff294d30d (diff) | |
| download | FOSSEE-netbook-kernel-source-871480933a1c28f8a9fed4c4d34d06c439a7a422.tar.gz FOSSEE-netbook-kernel-source-871480933a1c28f8a9fed4c4d34d06c439a7a422.tar.bz2 FOSSEE-netbook-kernel-source-871480933a1c28f8a9fed4c4d34d06c439a7a422.zip | |
Moved, renamed, and deleted files
The original directory structure was scattered and unorganized.
Changes are basically to make it look like kernel structure.
Diffstat (limited to 'ANDROID_3.4.5/arch/m68k/include/asm/mcfslt.h')
| -rw-r--r-- | ANDROID_3.4.5/arch/m68k/include/asm/mcfslt.h | 44 |
1 files changed, 0 insertions, 44 deletions
diff --git a/ANDROID_3.4.5/arch/m68k/include/asm/mcfslt.h b/ANDROID_3.4.5/arch/m68k/include/asm/mcfslt.h deleted file mode 100644 index d0d0ecba..00000000 --- a/ANDROID_3.4.5/arch/m68k/include/asm/mcfslt.h +++ /dev/null @@ -1,44 +0,0 @@ -/****************************************************************************/ - -/* - * mcfslt.h -- ColdFire internal Slice (SLT) timer support defines. - * - * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com) - * (C) Copyright 2009, Philippe De Muyter (phdm@macqel.be) - */ - -/****************************************************************************/ -#ifndef mcfslt_h -#define mcfslt_h -/****************************************************************************/ - -/* - * Get address specific defines for the 547x. - */ -#define MCFSLT_TIMER0 0x900 /* Base address of TIMER0 */ -#define MCFSLT_TIMER1 0x910 /* Base address of TIMER1 */ - - -/* - * Define the SLT timer register set addresses. - */ -#define MCFSLT_STCNT 0x00 /* Terminal count */ -#define MCFSLT_SCR 0x04 /* Control */ -#define MCFSLT_SCNT 0x08 /* Current count */ -#define MCFSLT_SSR 0x0C /* Status */ - -/* - * Bit definitions for the SCR control register. - */ -#define MCFSLT_SCR_RUN 0x04000000 /* Run mode (continuous) */ -#define MCFSLT_SCR_IEN 0x02000000 /* Interrupt enable */ -#define MCFSLT_SCR_TEN 0x01000000 /* Timer enable */ - -/* - * Bit definitions for the SSR status register. - */ -#define MCFSLT_SSR_BE 0x02000000 /* Bus error condition */ -#define MCFSLT_SSR_TE 0x01000000 /* Timeout condition */ - -/****************************************************************************/ -#endif /* mcfslt_h */ |