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author | Srikant Patnaik | 2015-01-11 12:28:04 +0530 |
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committer | Srikant Patnaik | 2015-01-11 12:28:04 +0530 |
commit | 871480933a1c28f8a9fed4c4d34d06c439a7a422 (patch) | |
tree | 8718f573808810c2a1e8cb8fb6ac469093ca2784 /ANDROID_3.4.5/arch/alpha/kernel/es1888.c | |
parent | 9d40ac5867b9aefe0722bc1f110b965ff294d30d (diff) | |
download | FOSSEE-netbook-kernel-source-871480933a1c28f8a9fed4c4d34d06c439a7a422.tar.gz FOSSEE-netbook-kernel-source-871480933a1c28f8a9fed4c4d34d06c439a7a422.tar.bz2 FOSSEE-netbook-kernel-source-871480933a1c28f8a9fed4c4d34d06c439a7a422.zip |
Moved, renamed, and deleted files
The original directory structure was scattered and unorganized.
Changes are basically to make it look like kernel structure.
Diffstat (limited to 'ANDROID_3.4.5/arch/alpha/kernel/es1888.c')
-rw-r--r-- | ANDROID_3.4.5/arch/alpha/kernel/es1888.c | 49 |
1 files changed, 0 insertions, 49 deletions
diff --git a/ANDROID_3.4.5/arch/alpha/kernel/es1888.c b/ANDROID_3.4.5/arch/alpha/kernel/es1888.c deleted file mode 100644 index d584c85f..00000000 --- a/ANDROID_3.4.5/arch/alpha/kernel/es1888.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * linux/arch/alpha/kernel/es1888.c - * - * Init the built-in ES1888 sound chip (SB16 compatible) - */ - -#include <linux/init.h> -#include <asm/io.h> -#include "proto.h" - -void __init -es1888_init(void) -{ - /* Sequence of IO reads to init the audio controller */ - inb(0x0229); - inb(0x0229); - inb(0x0229); - inb(0x022b); - inb(0x0229); - inb(0x022b); - inb(0x0229); - inb(0x0229); - inb(0x022b); - inb(0x0229); - inb(0x0220); /* This sets the base address to 0x220 */ - - /* Sequence to set DMA channels */ - outb(0x01, 0x0226); /* reset */ - inb(0x0226); /* pause */ - outb(0x00, 0x0226); /* release reset */ - while (!(inb(0x022e) & 0x80)) /* wait for bit 7 to assert*/ - continue; - inb(0x022a); /* pause */ - outb(0xc6, 0x022c); /* enable extended mode */ - inb(0x022a); /* pause, also forces the write */ - while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */ - continue; - outb(0xb1, 0x022c); /* setup for write to Interrupt CR */ - while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */ - continue; - outb(0x14, 0x022c); /* set IRQ 5 */ - while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */ - continue; - outb(0xb2, 0x022c); /* setup for write to DMA CR */ - while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */ - continue; - outb(0x18, 0x022c); /* set DMA channel 1 */ - inb(0x022c); /* force the write */ -} |