Add SN75160B IEEE-488 transceiver subcircuit

8 files changed, 1051 insertions, 0 deletions

diff --git a/library/SubcircuitLibrary/Sn75160b/Sn75160b-cache.lib b/library/SubcircuitLibrary/Sn75160b/Sn75160b-cache.lib
new file mode 100644
index 00000000..bf93b556
--- /dev/null
+++ b/library/SubcircuitLibrary/Sn75160b/Sn75160b-cache.lib
@@ -0,0 +1,103 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 P
+X ~ 2 250 0 100 L 30 30 2 1 P
+X ~ 3 250 0 100 L 30 30 3 1 P
+X ~ 4 250 0 100 L 30 30 4 1 P
+X ~ 5 250 0 100 L 30 30 5 1 P
+X ~ 6 250 0 100 L 30 30 6 1 P
+X ~ 7 250 0 100 L 30 30 7 1 P
+X ~ 8 250 0 100 L 30 30 8 1 P
+X ~ 9 250 0 100 L 30 30 9 1 P
+X ~ 10 250 0 100 L 30 30 10 1 P
+X ~ 11 250 0 100 L 30 30 11 1 P
+X ~ 12 250 0 100 L 30 30 12 1 P
+X ~ 13 250 0 100 L 30 30 13 1 P
+X ~ 14 250 0 100 L 30 30 14 1 P
+X ~ 15 250 0 100 L 30 30 15 1 P
+X ~ 16 250 0 100 L 30 30 16 1 P
+X ~ 17 250 0 100 L 30 30 17 1 P
+X ~ 18 250 0 100 L 30 30 18 1 P
+X ~ 19 250 0 100 L 30 30 19 1 P
+X ~ 20 250 0 100 L 30 30 20 1 P
+X ~ 21 250 0 100 L 30 30 21 1 P
+X ~ 22 250 0 100 L 30 30 22 1 P
+X ~ 23 250 0 100 L 30 30 23 1 P
+X ~ 24 250 0 100 L 30 30 24 1 P
+X ~ 25 250 0 100 L 30 30 25 1 P
+X ~ 26 250 0 100 L 30 30 26 1 P
+ENDDRAW
+ENDDEF
+#
+# buffer_4pin
+#
+DEF buffer_4pin U 0 40 Y Y 1 F N
+F0 "U" -100 -175 31 H V C CNN
+F1 "buffer_4pin" 175 -250 39 H V C CNN
+F2 "" 150 25 60 H V C CNN
+F3 "" 150 25 60 H V C CNN
+DRAW
+P 3 0 1 0 -25 150 350 -25 -25 -200 N
+P 4 0 1 0 -25 -200 -175 -275 -175 225 -25 150 N
+X A0 1 -375 -25 200 R 50 31 1 1 B
+X VCC 2 -25 350 200 D 50 31 1 1 I
+X GND 3 -25 -400 200 U 50 31 1 1 I N
+X Y0 4 550 -25 200 L 50 31 1 1 B
+ENDDRAW
+ENDDEF
+#
+# d_buffer
+#
+DEF d_buffer U 0 40 Y Y 1 F N
+F0 "U" 0 -50 60 H V C CNN
+F1 "d_buffer" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N
+X IN 1 -500 0 200 R 50 50 1 1 I
+X OUT 2 650 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# tristate_buffer_active_low
+#
+DEF tristate_buffer_active_low U 0 40 Y Y 1 F N
+F0 "U" -75 -175 60 H V C CNN
+F1 "tristate_buffer_active_low" 325 -125 31 H V C CNN
+F2 "" 0 100 60 H V C CNN
+F3 "" 0 100 60 H V C CNN
+DRAW
+P 5 0 1 0 -250 300 0 200 425 50 -250 -150 -250 300 N
+X A0 1 -450 25 200 R 50 50 1 1 B
+X EN0 2 0 400 200 D 50 50 1 1 I
+X Y0 3 625 50 200 L 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/Sn75160b/Sn75160b.cir b/library/SubcircuitLibrary/Sn75160b/Sn75160b.cir
new file mode 100644
index 00000000..5ba50773
--- /dev/null
+++ b/library/SubcircuitLibrary/Sn75160b/Sn75160b.cir
@@ -0,0 +1,29 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\Sn75160b\Sn75160b.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 04/12/25 13:54:31
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U8  Net-_U1-Pad8_ /TE Net-_U1-Pad3_ tristate_buffer_active_low		
+U4  Net-_U1-Pad3_ /PE ? Net-_U1-Pad8_ buffer_4pin		
+U2  Net-_U1-Pad1_ /PE d_buffer		
+U3  Net-_U1-Pad2_ /TE d_buffer		
+U9  Net-_U1-Pad7_ /TE Net-_U1-Pad4_ tristate_buffer_active_low		
+U5  Net-_U1-Pad4_ /PE ? Net-_U1-Pad7_ buffer_4pin		
+U10  Net-_U1-Pad9_ /TE Net-_U1-Pad5_ tristate_buffer_active_low		
+U6  Net-_U1-Pad5_ /PE ? Net-_U1-Pad9_ buffer_4pin		
+U11  Net-_U1-Pad10_ /TE Net-_U1-Pad6_ tristate_buffer_active_low		
+U7  Net-_U1-Pad6_ /PE ? Net-_U1-Pad10_ buffer_4pin		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ GND GND PORT		
+U16  Net-_U1-Pad16_ /TE Net-_U1-Pad11_ tristate_buffer_active_low		
+U12  Net-_U1-Pad11_ /PE ? Net-_U1-Pad16_ buffer_4pin		
+U17  Net-_U1-Pad15_ /TE Net-_U1-Pad12_ tristate_buffer_active_low		
+U13  Net-_U1-Pad12_ /PE ? Net-_U1-Pad15_ buffer_4pin		
+U18  Net-_U1-Pad17_ /TE Net-_U1-Pad13_ tristate_buffer_active_low		
+U14  Net-_U1-Pad13_ /PE ? Net-_U1-Pad17_ buffer_4pin		
+U19  Net-_U1-Pad18_ /TE Net-_U1-Pad14_ tristate_buffer_active_low		
+U15  Net-_U1-Pad14_ /PE ? Net-_U1-Pad18_ buffer_4pin		
+
+.end
diff --git a/library/SubcircuitLibrary/Sn75160b/Sn75160b.cir.out b/library/SubcircuitLibrary/Sn75160b/Sn75160b.cir.out
new file mode 100644
index 00000000..ba93807c
--- /dev/null
+++ b/library/SubcircuitLibrary/Sn75160b/Sn75160b.cir.out
@@ -0,0 +1,84 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn75160b\sn75160b.cir
+
+* u8  net-_u1-pad8_ /te net-_u1-pad3_ tristate_buffer_active_low
+* u4  net-_u1-pad3_ /pe ? net-_u1-pad8_ buffer_4pin
+* u2  net-_u1-pad1_ /pe d_buffer
+* u3  net-_u1-pad2_ /te d_buffer
+* u9  net-_u1-pad7_ /te net-_u1-pad4_ tristate_buffer_active_low
+* u5  net-_u1-pad4_ /pe ? net-_u1-pad7_ buffer_4pin
+* u10  net-_u1-pad9_ /te net-_u1-pad5_ tristate_buffer_active_low
+* u6  net-_u1-pad5_ /pe ? net-_u1-pad9_ buffer_4pin
+* u11  net-_u1-pad10_ /te net-_u1-pad6_ tristate_buffer_active_low
+* u7  net-_u1-pad6_ /pe ? net-_u1-pad10_ buffer_4pin
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ gnd gnd port
+* u16  net-_u1-pad16_ /te net-_u1-pad11_ tristate_buffer_active_low
+* u12  net-_u1-pad11_ /pe ? net-_u1-pad16_ buffer_4pin
+* u17  net-_u1-pad15_ /te net-_u1-pad12_ tristate_buffer_active_low
+* u13  net-_u1-pad12_ /pe ? net-_u1-pad15_ buffer_4pin
+* u18  net-_u1-pad17_ /te net-_u1-pad13_ tristate_buffer_active_low
+* u14  net-_u1-pad13_ /pe ? net-_u1-pad17_ buffer_4pin
+* u19  net-_u1-pad18_ /te net-_u1-pad14_ tristate_buffer_active_low
+* u15  net-_u1-pad14_ /pe ? net-_u1-pad18_ buffer_4pin
+a1 [net-_u1-pad8_ ] [/te ] [net-_u1-pad3_ ] u8
+a2 [net-_u1-pad3_ ] [/pe ] [? ] [net-_u1-pad8_ ] u4
+a3 net-_u1-pad1_ /pe u2
+a4 net-_u1-pad2_ /te u3
+a5 [net-_u1-pad7_ ] [/te ] [net-_u1-pad4_ ] u9
+a6 [net-_u1-pad4_ ] [/pe ] [? ] [net-_u1-pad7_ ] u5
+a7 [net-_u1-pad9_ ] [/te ] [net-_u1-pad5_ ] u10
+a8 [net-_u1-pad5_ ] [/pe ] [? ] [net-_u1-pad9_ ] u6
+a9 [net-_u1-pad10_ ] [/te ] [net-_u1-pad6_ ] u11
+a10 [net-_u1-pad6_ ] [/pe ] [? ] [net-_u1-pad10_ ] u7
+a11 [net-_u1-pad16_ ] [/te ] [net-_u1-pad11_ ] u16
+a12 [net-_u1-pad11_ ] [/pe ] [? ] [net-_u1-pad16_ ] u12
+a13 [net-_u1-pad15_ ] [/te ] [net-_u1-pad12_ ] u17
+a14 [net-_u1-pad12_ ] [/pe ] [? ] [net-_u1-pad15_ ] u13
+a15 [net-_u1-pad17_ ] [/te ] [net-_u1-pad13_ ] u18
+a16 [net-_u1-pad13_ ] [/pe ] [? ] [net-_u1-pad17_ ] u14
+a17 [net-_u1-pad18_ ] [/te ] [net-_u1-pad14_ ] u19
+a18 [net-_u1-pad14_ ] [/pe ] [? ] [net-_u1-pad18_ ] u15
+* Schematic Name:                             tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
+.model u8 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             buffer_4pin, NgSpice Name: buffer_4pin
+.model u4 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             d_buffer, NgSpice Name: d_buffer
+.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_buffer, NgSpice Name: d_buffer
+.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
+.model u9 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             buffer_4pin, NgSpice Name: buffer_4pin
+.model u5 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
+.model u10 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             buffer_4pin, NgSpice Name: buffer_4pin
+.model u6 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
+.model u11 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             buffer_4pin, NgSpice Name: buffer_4pin
+.model u7 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
+.model u16 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             buffer_4pin, NgSpice Name: buffer_4pin
+.model u12 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
+.model u17 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             buffer_4pin, NgSpice Name: buffer_4pin
+.model u13 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
+.model u18 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             buffer_4pin, NgSpice Name: buffer_4pin
+.model u14 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
+.model u19 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             buffer_4pin, NgSpice Name: buffer_4pin
+.model u15 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/Sn75160b/Sn75160b.pro b/library/SubcircuitLibrary/Sn75160b/Sn75160b.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/Sn75160b/Sn75160b.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/Sn75160b/Sn75160b.sch b/library/SubcircuitLibrary/Sn75160b/Sn75160b.sch
new file mode 100644
index 00000000..adecf4be
--- /dev/null
+++ b/library/SubcircuitLibrary/Sn75160b/Sn75160b.sch
@@ -0,0 +1,682 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L tristate_buffer_active_low U8
+U 1 1 67FA2026
+P 3625 3175
+F 0 "U8" H 3550 3000 60  0000 C CNN
+F 1 "tristate_buffer_active_low" H 3950 3050 31  0000 C CNN
+F 2 "" H 3625 3275 60  0000 C CNN
+F 3 "" H 3625 3275 60  0000 C CNN
+	1    3625 3175
+	-1   0    0    -1  
+$EndComp
+$Comp
+L buffer_4pin U4
+U 1 1 67FA20A9
+P 3375 2350
+F 0 "U4" H 3275 2175 31  0000 C CNN
+F 1 "buffer_4pin" H 3550 2100 39  0000 C CNN
+F 2 "" H 3525 2375 60  0000 C CNN
+F 3 "" H 3525 2375 60  0000 C CNN
+	1    3375 2350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_buffer U2
+U 1 1 67FA2105
+P 1900 1275
+F 0 "U2" H 1900 1225 60  0000 C CNN
+F 1 "d_buffer" H 1900 1325 60  0000 C CNN
+F 2 "" H 1900 1275 60  0000 C CNN
+F 3 "" H 1900 1275 60  0000 C CNN
+	1    1900 1275
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_buffer U3
+U 1 1 67FA213B
+P 1900 1800
+F 0 "U3" H 1900 1750 60  0000 C CNN
+F 1 "d_buffer" H 1900 1850 60  0000 C CNN
+F 2 "" H 1900 1800 60  0000 C CNN
+F 3 "" H 1900 1800 60  0000 C CNN
+	1    1900 1800
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3350 2000 4550 2000
+Wire Wire Line
+	1775 2375 3000 2375
+Wire Wire Line
+	2550 1800 2600 1800
+Wire Wire Line
+	2600 1800 2600 7225
+Wire Wire Line
+	2600 2775 3625 2775
+Wire Wire Line
+	3000 3125 2850 3125
+Wire Wire Line
+	2850 3125 2850 2375
+Connection ~ 2850 2375
+Wire Wire Line
+	4075 3150 4775 3150
+Wire Wire Line
+	3925 2375 4175 2375
+Wire Wire Line
+	4175 2375 4175 3150
+Connection ~ 4175 3150
+$Comp
+L tristate_buffer_active_low U9
+U 1 1 67FA23A9
+P 3675 4675
+F 0 "U9" H 3600 4500 60  0000 C CNN
+F 1 "tristate_buffer_active_low" H 4000 4550 31  0000 C CNN
+F 2 "" H 3675 4775 60  0000 C CNN
+F 3 "" H 3675 4775 60  0000 C CNN
+	1    3675 4675
+	-1   0    0    -1  
+$EndComp
+$Comp
+L buffer_4pin U5
+U 1 1 67FA23AF
+P 3425 3850
+F 0 "U5" H 3325 3675 31  0000 C CNN
+F 1 "buffer_4pin" H 3600 3600 39  0000 C CNN
+F 2 "" H 3575 3875 60  0000 C CNN
+F 3 "" H 3575 3875 60  0000 C CNN
+	1    3425 3850
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2600 4275 3675 4275
+Wire Wire Line
+	2200 3875 3050 3875
+Wire Wire Line
+	2200 3875 2200 3900
+Wire Wire Line
+	3050 4625 2800 4625
+Wire Wire Line
+	2800 4625 2800 3875
+Connection ~ 2800 3875
+Wire Wire Line
+	4125 4650 4675 4650
+Wire Wire Line
+	3975 3875 4275 3875
+Wire Wire Line
+	4275 3875 4275 4650
+Connection ~ 4275 4650
+$Comp
+L tristate_buffer_active_low U10
+U 1 1 67FA2560
+P 3775 6175
+F 0 "U10" H 3700 6000 60  0000 C CNN
+F 1 "tristate_buffer_active_low" H 4100 6050 31  0000 C CNN
+F 2 "" H 3775 6275 60  0000 C CNN
+F 3 "" H 3775 6275 60  0000 C CNN
+	1    3775 6175
+	-1   0    0    -1  
+$EndComp
+$Comp
+L buffer_4pin U6
+U 1 1 67FA2566
+P 3525 5350
+F 0 "U6" H 3425 5175 31  0000 C CNN
+F 1 "buffer_4pin" H 3700 5100 39  0000 C CNN
+F 2 "" H 3675 5375 60  0000 C CNN
+F 3 "" H 3675 5375 60  0000 C CNN
+	1    3525 5350
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2600 5775 3775 5775
+Wire Wire Line
+	2300 5375 3150 5375
+Wire Wire Line
+	2300 5375 2300 5400
+Wire Wire Line
+	3150 6125 2900 6125
+Wire Wire Line
+	2900 6125 2900 5375
+Connection ~ 2900 5375
+Wire Wire Line
+	4225 6150 4775 6150
+Wire Wire Line
+	4075 5375 4375 5375
+Wire Wire Line
+	4375 5375 4375 6150
+Connection ~ 4375 6150
+$Comp
+L tristate_buffer_active_low U11
+U 1 1 67FA26AE
+P 3775 7625
+F 0 "U11" H 3700 7450 60  0000 C CNN
+F 1 "tristate_buffer_active_low" H 4100 7500 31  0000 C CNN
+F 2 "" H 3775 7725 60  0000 C CNN
+F 3 "" H 3775 7725 60  0000 C CNN
+	1    3775 7625
+	-1   0    0    -1  
+$EndComp
+$Comp
+L buffer_4pin U7
+U 1 1 67FA26B4
+P 3525 6800
+F 0 "U7" H 3425 6625 31  0000 C CNN
+F 1 "buffer_4pin" H 3700 6550 39  0000 C CNN
+F 2 "" H 3675 6825 60  0000 C CNN
+F 3 "" H 3675 6825 60  0000 C CNN
+	1    3525 6800
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2600 7225 3775 7225
+Wire Wire Line
+	2300 6825 3150 6825
+Wire Wire Line
+	2300 6825 2300 6850
+Wire Wire Line
+	3150 7575 2900 7575
+Wire Wire Line
+	2900 7575 2900 6825
+Connection ~ 2900 6825
+Wire Wire Line
+	4225 7600 4775 7600
+Wire Wire Line
+	4075 6825 4375 6825
+Wire Wire Line
+	4375 6825 4375 7600
+Connection ~ 4375 7600
+Connection ~ 2600 2775
+Connection ~ 2600 4275
+Connection ~ 2600 5775
+Wire Wire Line
+	2550 1275 4550 1275
+Wire Wire Line
+	4550 1275 4550 6450
+Wire Wire Line
+	4550 6450 3500 6450
+Connection ~ 4550 2000
+Wire Wire Line
+	3500 5000 4550 5000
+Connection ~ 4550 5000
+Wire Wire Line
+	3400 3500 4550 3500
+Connection ~ 4550 3500
+Wire Wire Line
+	1400 1275 1025 1275
+Wire Wire Line
+	1400 1800 1050 1800
+$Comp
+L PORT U1
+U 1 1 67FA2EEE
+P 775 1275
+F 0 "U1" H 825 1375 30  0000 C CNN
+F 1 "PORT" H 775 1275 30  0000 C CNN
+F 2 "" H 775 1275 60  0000 C CNN
+F 3 "" H 775 1275 60  0000 C CNN
+	1    775  1275
+	1    0    0    -1  
+$EndComp
+$Comp
+L tristate_buffer_active_low U16
+U 1 1 67FA35AF
+P 7450 2450
+F 0 "U16" H 7375 2275 60  0000 C CNN
+F 1 "tristate_buffer_active_low" H 7775 2325 31  0000 C CNN
+F 2 "" H 7450 2550 60  0000 C CNN
+F 3 "" H 7450 2550 60  0000 C CNN
+	1    7450 2450
+	-1   0    0    -1  
+$EndComp
+$Comp
+L buffer_4pin U12
+U 1 1 67FA35B5
+P 7200 1625
+F 0 "U12" H 7100 1450 31  0000 C CNN
+F 1 "buffer_4pin" H 7375 1375 39  0000 C CNN
+F 2 "" H 7350 1650 60  0000 C CNN
+F 3 "" H 7350 1650 60  0000 C CNN
+	1    7200 1625
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5925 1650 6825 1650
+Wire Wire Line
+	6425 1175 6425 6500
+Wire Wire Line
+	6425 2050 7450 2050
+Wire Wire Line
+	6825 2400 6675 2400
+Wire Wire Line
+	6675 2400 6675 1650
+Connection ~ 6675 1650
+Wire Wire Line
+	7900 2425 8600 2425
+Wire Wire Line
+	7750 1650 8000 1650
+Wire Wire Line
+	8000 1650 8000 2425
+Connection ~ 8000 2425
+$Comp
+L tristate_buffer_active_low U17
+U 1 1 67FA35C5
+P 7500 3950
+F 0 "U17" H 7425 3775 60  0000 C CNN
+F 1 "tristate_buffer_active_low" H 7825 3825 31  0000 C CNN
+F 2 "" H 7500 4050 60  0000 C CNN
+F 3 "" H 7500 4050 60  0000 C CNN
+	1    7500 3950
+	-1   0    0    -1  
+$EndComp
+$Comp
+L buffer_4pin U13
+U 1 1 67FA35CB
+P 7250 3125
+F 0 "U13" H 7150 2950 31  0000 C CNN
+F 1 "buffer_4pin" H 7425 2875 39  0000 C CNN
+F 2 "" H 7400 3150 60  0000 C CNN
+F 3 "" H 7400 3150 60  0000 C CNN
+	1    7250 3125
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6425 3550 7500 3550
+Wire Wire Line
+	6025 3150 6875 3150
+Wire Wire Line
+	6875 3900 6625 3900
+Wire Wire Line
+	6625 3900 6625 3150
+Connection ~ 6625 3150
+Wire Wire Line
+	7950 3925 8500 3925
+Wire Wire Line
+	7800 3150 8100 3150
+Wire Wire Line
+	8100 3150 8100 3925
+Connection ~ 8100 3925
+$Comp
+L tristate_buffer_active_low U18
+U 1 1 67FA35DA
+P 7600 5450
+F 0 "U18" H 7525 5275 60  0000 C CNN
+F 1 "tristate_buffer_active_low" H 7925 5325 31  0000 C CNN
+F 2 "" H 7600 5550 60  0000 C CNN
+F 3 "" H 7600 5550 60  0000 C CNN
+	1    7600 5450
+	-1   0    0    -1  
+$EndComp
+$Comp
+L buffer_4pin U14
+U 1 1 67FA35E0
+P 7350 4625
+F 0 "U14" H 7250 4450 31  0000 C CNN
+F 1 "buffer_4pin" H 7525 4375 39  0000 C CNN
+F 2 "" H 7500 4650 60  0000 C CNN
+F 3 "" H 7500 4650 60  0000 C CNN
+	1    7350 4625
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6425 5050 7600 5050
+Wire Wire Line
+	6125 4650 6975 4650
+Wire Wire Line
+	6975 5400 6725 5400
+Wire Wire Line
+	6725 5400 6725 4650
+Connection ~ 6725 4650
+Wire Wire Line
+	8050 5425 8600 5425
+Wire Wire Line
+	7900 4650 8200 4650
+Wire Wire Line
+	8200 4650 8200 5425
+Connection ~ 8200 5425
+$Comp
+L tristate_buffer_active_low U19
+U 1 1 67FA35EF
+P 7600 6900
+F 0 "U19" H 7525 6725 60  0000 C CNN
+F 1 "tristate_buffer_active_low" H 7925 6775 31  0000 C CNN
+F 2 "" H 7600 7000 60  0000 C CNN
+F 3 "" H 7600 7000 60  0000 C CNN
+	1    7600 6900
+	-1   0    0    -1  
+$EndComp
+$Comp
+L buffer_4pin U15
+U 1 1 67FA35F5
+P 7350 6075
+F 0 "U15" H 7250 5900 31  0000 C CNN
+F 1 "buffer_4pin" H 7525 5825 39  0000 C CNN
+F 2 "" H 7500 6100 60  0000 C CNN
+F 3 "" H 7500 6100 60  0000 C CNN
+	1    7350 6075
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6425 6500 7600 6500
+Wire Wire Line
+	6125 6100 6975 6100
+Wire Wire Line
+	6975 6850 6725 6850
+Wire Wire Line
+	6725 6850 6725 6100
+Connection ~ 6725 6100
+Wire Wire Line
+	8050 6875 8600 6875
+Wire Wire Line
+	7900 6100 8200 6100
+Wire Wire Line
+	8200 6100 8200 6875
+Connection ~ 8200 6875
+Connection ~ 6425 2050
+Connection ~ 6425 3550
+Connection ~ 6425 5050
+Wire Wire Line
+	8375 1200 8375 5725
+Wire Wire Line
+	8375 5725 7325 5725
+Wire Wire Line
+	7325 4275 8375 4275
+Connection ~ 8375 4275
+Wire Wire Line
+	7225 2775 8375 2775
+Connection ~ 8375 2775
+$Comp
+L PORT U1
+U 8 1 67FA3AB8
+P 5025 3150
+F 0 "U1" H 5075 3250 30  0000 C CNN
+F 1 "PORT" H 5025 3150 30  0000 C CNN
+F 2 "" H 5025 3150 60  0000 C CNN
+F 3 "" H 5025 3150 60  0000 C CNN
+	8    5025 3150
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 7 1 67FA3C3D
+P 4925 4650
+F 0 "U1" H 4975 4750 30  0000 C CNN
+F 1 "PORT" H 4925 4650 30  0000 C CNN
+F 2 "" H 4925 4650 60  0000 C CNN
+F 3 "" H 4925 4650 60  0000 C CNN
+	7    4925 4650
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 9 1 67FA3DC7
+P 5025 6150
+F 0 "U1" H 5075 6250 30  0000 C CNN
+F 1 "PORT" H 5025 6150 30  0000 C CNN
+F 2 "" H 5025 6150 60  0000 C CNN
+F 3 "" H 5025 6150 60  0000 C CNN
+	9    5025 6150
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 10 1 67FA3EEE
+P 5025 7600
+F 0 "U1" H 5075 7700 30  0000 C CNN
+F 1 "PORT" H 5025 7600 30  0000 C CNN
+F 2 "" H 5025 7600 60  0000 C CNN
+F 3 "" H 5025 7600 60  0000 C CNN
+	10   5025 7600
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 16 1 67FA4049
+P 8850 2425
+F 0 "U1" H 8900 2525 30  0000 C CNN
+F 1 "PORT" H 8850 2425 30  0000 C CNN
+F 2 "" H 8850 2425 60  0000 C CNN
+F 3 "" H 8850 2425 60  0000 C CNN
+	16   8850 2425
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 15 1 67FA4226
+P 8750 3925
+F 0 "U1" H 8800 4025 30  0000 C CNN
+F 1 "PORT" H 8750 3925 30  0000 C CNN
+F 2 "" H 8750 3925 60  0000 C CNN
+F 3 "" H 8750 3925 60  0000 C CNN
+	15   8750 3925
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 17 1 67FA4356
+P 8850 5425
+F 0 "U1" H 8900 5525 30  0000 C CNN
+F 1 "PORT" H 8850 5425 30  0000 C CNN
+F 2 "" H 8850 5425 60  0000 C CNN
+F 3 "" H 8850 5425 60  0000 C CNN
+	17   8850 5425
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 18 1 67FA4589
+P 8850 6875
+F 0 "U1" H 8900 6975 30  0000 C CNN
+F 1 "PORT" H 8850 6875 30  0000 C CNN
+F 2 "" H 8850 6875 60  0000 C CNN
+F 3 "" H 8850 6875 60  0000 C CNN
+	18   8850 6875
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 19 1 67FA473F
+P 9750 2275
+F 0 "U1" H 9800 2375 30  0000 C CNN
+F 1 "PORT" H 9750 2275 30  0000 C CNN
+F 2 "" H 9750 2275 60  0000 C CNN
+F 3 "" H 9750 2275 60  0000 C CNN
+	19   9750 2275
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 67FA485A
+P 800 1800
+F 0 "U1" H 850 1900 30  0000 C CNN
+F 1 "PORT" H 800 1800 30  0000 C CNN
+F 2 "" H 800 1800 60  0000 C CNN
+F 3 "" H 800 1800 60  0000 C CNN
+	2    800  1800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 14 1 67FA4CFD
+P 5875 6100
+F 0 "U1" H 5925 6200 30  0000 C CNN
+F 1 "PORT" H 5875 6100 30  0000 C CNN
+F 2 "" H 5875 6100 60  0000 C CNN
+F 3 "" H 5875 6100 60  0000 C CNN
+	14   5875 6100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 13 1 67FA514E
+P 5875 4650
+F 0 "U1" H 5925 4750 30  0000 C CNN
+F 1 "PORT" H 5875 4650 30  0000 C CNN
+F 2 "" H 5875 4650 60  0000 C CNN
+F 3 "" H 5875 4650 60  0000 C CNN
+	13   5875 4650
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 12 1 67FA526B
+P 5775 3150
+F 0 "U1" H 5825 3250 30  0000 C CNN
+F 1 "PORT" H 5775 3150 30  0000 C CNN
+F 2 "" H 5775 3150 60  0000 C CNN
+F 3 "" H 5775 3150 60  0000 C CNN
+	12   5775 3150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 11 1 67FA574A
+P 5675 1650
+F 0 "U1" H 5725 1750 30  0000 C CNN
+F 1 "PORT" H 5675 1650 30  0000 C CNN
+F 2 "" H 5675 1650 60  0000 C CNN
+F 3 "" H 5675 1650 60  0000 C CNN
+	11   5675 1650
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 67FA58D8
+P 2050 6850
+F 0 "U1" H 2100 6950 30  0000 C CNN
+F 1 "PORT" H 2050 6850 30  0000 C CNN
+F 2 "" H 2050 6850 60  0000 C CNN
+F 3 "" H 2050 6850 60  0000 C CNN
+	6    2050 6850
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 67FA5B41
+P 2050 5400
+F 0 "U1" H 2100 5500 30  0000 C CNN
+F 1 "PORT" H 2050 5400 30  0000 C CNN
+F 2 "" H 2050 5400 60  0000 C CNN
+F 3 "" H 2050 5400 60  0000 C CNN
+	5    2050 5400
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 67FA5D52
+P 1950 3900
+F 0 "U1" H 2000 4000 30  0000 C CNN
+F 1 "PORT" H 1950 3900 30  0000 C CNN
+F 2 "" H 1950 3900 60  0000 C CNN
+F 3 "" H 1950 3900 60  0000 C CNN
+	4    1950 3900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 67FA5F93
+P 1525 2375
+F 0 "U1" H 1575 2475 30  0000 C CNN
+F 1 "PORT" H 1525 2375 30  0000 C CNN
+F 2 "" H 1525 2375 60  0000 C CNN
+F 3 "" H 1525 2375 60  0000 C CNN
+	3    1525 2375
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 20 1 67FA6271
+P 9750 2575
+F 0 "U1" H 9800 2675 30  0000 C CNN
+F 1 "PORT" H 9750 2575 30  0000 C CNN
+F 2 "" H 9750 2575 60  0000 C CNN
+F 3 "" H 9750 2575 60  0000 C CNN
+	20   9750 2575
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	10000 2275 10175 2275
+Wire Wire Line
+	10175 2275 10175 2575
+Wire Wire Line
+	10175 2575 10000 2575
+$Comp
+L eSim_GND #PWR01
+U 1 1 67FA6444
+P 10325 2425
+F 0 "#PWR01" H 10325 2175 50  0001 C CNN
+F 1 "eSim_GND" H 10325 2275 50  0000 C CNN
+F 2 "" H 10325 2425 50  0001 C CNN
+F 3 "" H 10325 2425 50  0001 C CNN
+	1    10325 2425
+	0    -1   -1   0   
+$EndComp
+Wire Wire Line
+	10325 2425 10175 2425
+Connection ~ 10175 2425
+Text Label 2600 2025 0    60   ~ 0
+TE
+Text Label 3050 1275 0    60   ~ 0
+PE
+Wire Wire Line
+	6425 1175 6450 1175
+Wire Wire Line
+	7175 1275 8375 1275
+Connection ~ 8375 1275
+Text Label 6450 1175 0    60   ~ 0
+TE
+Text Label 8375 1200 0    60   ~ 0
+PE
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/Sn75160b/Sn75160b.sub b/library/SubcircuitLibrary/Sn75160b/Sn75160b.sub
new file mode 100644
index 00000000..fa8e1b0c
--- /dev/null
+++ b/library/SubcircuitLibrary/Sn75160b/Sn75160b.sub
@@ -0,0 +1,78 @@
+* Subcircuit Sn75160b
+.subckt Sn75160b net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ gnd gnd 
+* c:\fossee\esim\library\subcircuitlibrary\sn75160b\sn75160b.cir
+* u8  net-_u1-pad8_ /te net-_u1-pad3_ tristate_buffer_active_low
+* u4  net-_u1-pad3_ /pe ? net-_u1-pad8_ buffer_4pin
+* u2  net-_u1-pad1_ /pe d_buffer
+* u3  net-_u1-pad2_ /te d_buffer
+* u9  net-_u1-pad7_ /te net-_u1-pad4_ tristate_buffer_active_low
+* u5  net-_u1-pad4_ /pe ? net-_u1-pad7_ buffer_4pin
+* u10  net-_u1-pad9_ /te net-_u1-pad5_ tristate_buffer_active_low
+* u6  net-_u1-pad5_ /pe ? net-_u1-pad9_ buffer_4pin
+* u11  net-_u1-pad10_ /te net-_u1-pad6_ tristate_buffer_active_low
+* u7  net-_u1-pad6_ /pe ? net-_u1-pad10_ buffer_4pin
+* u16  net-_u1-pad16_ /te net-_u1-pad11_ tristate_buffer_active_low
+* u12  net-_u1-pad11_ /pe ? net-_u1-pad16_ buffer_4pin
+* u17  net-_u1-pad15_ /te net-_u1-pad12_ tristate_buffer_active_low
+* u13  net-_u1-pad12_ /pe ? net-_u1-pad15_ buffer_4pin
+* u18  net-_u1-pad17_ /te net-_u1-pad13_ tristate_buffer_active_low
+* u14  net-_u1-pad13_ /pe ? net-_u1-pad17_ buffer_4pin
+* u19  net-_u1-pad18_ /te net-_u1-pad14_ tristate_buffer_active_low
+* u15  net-_u1-pad14_ /pe ? net-_u1-pad18_ buffer_4pin
+a1 [net-_u1-pad8_ ] [/te ] [net-_u1-pad3_ ] u8
+a2 [net-_u1-pad3_ ] [/pe ] [? ] [net-_u1-pad8_ ] u4
+a3 net-_u1-pad1_ /pe u2
+a4 net-_u1-pad2_ /te u3
+a5 [net-_u1-pad7_ ] [/te ] [net-_u1-pad4_ ] u9
+a6 [net-_u1-pad4_ ] [/pe ] [? ] [net-_u1-pad7_ ] u5
+a7 [net-_u1-pad9_ ] [/te ] [net-_u1-pad5_ ] u10
+a8 [net-_u1-pad5_ ] [/pe ] [? ] [net-_u1-pad9_ ] u6
+a9 [net-_u1-pad10_ ] [/te ] [net-_u1-pad6_ ] u11
+a10 [net-_u1-pad6_ ] [/pe ] [? ] [net-_u1-pad10_ ] u7
+a11 [net-_u1-pad16_ ] [/te ] [net-_u1-pad11_ ] u16
+a12 [net-_u1-pad11_ ] [/pe ] [? ] [net-_u1-pad16_ ] u12
+a13 [net-_u1-pad15_ ] [/te ] [net-_u1-pad12_ ] u17
+a14 [net-_u1-pad12_ ] [/pe ] [? ] [net-_u1-pad15_ ] u13
+a15 [net-_u1-pad17_ ] [/te ] [net-_u1-pad13_ ] u18
+a16 [net-_u1-pad13_ ] [/pe ] [? ] [net-_u1-pad17_ ] u14
+a17 [net-_u1-pad18_ ] [/te ] [net-_u1-pad14_ ] u19
+a18 [net-_u1-pad14_ ] [/pe ] [? ] [net-_u1-pad18_ ] u15
+* Schematic Name:                             tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
+.model u8 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name:                             buffer_4pin, NgSpice Name: buffer_4pin
+.model u4 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name:                             d_buffer, NgSpice Name: d_buffer
+.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_buffer, NgSpice Name: d_buffer
+.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
+.model u9 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name:                             buffer_4pin, NgSpice Name: buffer_4pin
+.model u5 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name:                             tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
+.model u10 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name:                             buffer_4pin, NgSpice Name: buffer_4pin
+.model u6 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name:                             tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
+.model u11 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name:                             buffer_4pin, NgSpice Name: buffer_4pin
+.model u7 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name:                             tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
+.model u16 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name:                             buffer_4pin, NgSpice Name: buffer_4pin
+.model u12 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name:                             tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
+.model u17 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name:                             buffer_4pin, NgSpice Name: buffer_4pin
+.model u13 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name:                             tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
+.model u18 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name:                             buffer_4pin, NgSpice Name: buffer_4pin
+.model u14 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name:                             tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
+.model u19 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name:                             buffer_4pin, NgSpice Name: buffer_4pin
+.model u15 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Control Statements
+
+.ends Sn75160b
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/Sn75160b/Sn75160b_Previous_Values.xml b/library/SubcircuitLibrary/Sn75160b/Sn75160b_Previous_Values.xml
new file mode 100644
index 00000000..41acd581
--- /dev/null
+++ b/library/SubcircuitLibrary/Sn75160b/Sn75160b_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u8 name="type">tristate_buffer_active_low<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /><field4 name="Enter Instance ID (Between 0-99)" /></u8><u4 name="type">buffer_4pin<field5 name="Enter Rise Delay (default=1.0e-9)" /><field6 name="Enter Fall Delay (default=1.0e-9)" /><field7 name="Enter Input Load (default=1.0e-12)" /><field8 name="Enter Instance ID (Between 0-99)" /></u4><u2 name="type">d_buffer<field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_buffer<field12 name="Enter Rise Delay (default=1.0e-9)" /><field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /></u3><u9 name="type">tristate_buffer_active_low<field15 name="Enter Rise Delay (default=1.0e-9)" /><field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Instance ID (Between 0-99)" /></u9><u5 name="type">buffer_4pin<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /><field22 name="Enter Instance ID (Between 0-99)" /></u5><u10 name="type">tristate_buffer_active_low<field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /><field25 name="Enter Input Load (default=1.0e-12)" /><field26 name="Enter Instance ID (Between 0-99)" /></u10><u6 name="type">buffer_4pin<field27 name="Enter Rise Delay (default=1.0e-9)" /><field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Instance ID (Between 0-99)" /></u6><u11 name="type">tristate_buffer_active_low<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /><field34 name="Enter Instance ID (Between 0-99)" /></u11><u7 name="type">buffer_4pin<field35 name="Enter Rise Delay (default=1.0e-9)" /><field36 name="Enter Fall Delay (default=1.0e-9)" /><field37 name="Enter Input Load (default=1.0e-12)" /><field38 name="Enter Instance ID (Between 0-99)" /></u7><u16 name="type">tristate_buffer_active_low<field39 name="Enter Rise Delay (default=1.0e-9)" /><field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Instance ID (Between 0-99)" /></u16><u12 name="type">buffer_4pin<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /><field46 name="Enter Instance ID (Between 0-99)" /></u12><u17 name="type">tristate_buffer_active_low<field47 name="Enter Rise Delay (default=1.0e-9)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /><field49 name="Enter Input Load (default=1.0e-12)" /><field50 name="Enter Instance ID (Between 0-99)" /></u17><u13 name="type">buffer_4pin<field51 name="Enter Rise Delay (default=1.0e-9)" /><field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Instance ID (Between 0-99)" /></u13><u18 name="type">tristate_buffer_active_low<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /><field58 name="Enter Instance ID (Between 0-99)" /></u18><u14 name="type">buffer_4pin<field59 name="Enter Rise Delay (default=1.0e-9)" /><field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /><field62 name="Enter Instance ID (Between 0-99)" /></u14><u19 name="type">tristate_buffer_active_low<field63 name="Enter Rise Delay (default=1.0e-9)" /><field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Instance ID (Between 0-99)" /></u19><u15 name="type">buffer_4pin<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /><field70 name="Enter Instance ID (Between 0-99)" /></u15></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/Sn75160b/analysis b/library/SubcircuitLibrary/Sn75160b/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/Sn75160b/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file