Add SN74LVC257A quad 2:1 multiplexer subcircuit

8 files changed, 941 insertions, 0 deletions

diff --git a/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A-cache.lib b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A-cache.lib
new file mode 100644
index 00000000..136c4de9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A-cache.lib
@@ -0,0 +1,123 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 P
+X ~ 2 250 0 100 L 30 30 2 1 P
+X ~ 3 250 0 100 L 30 30 3 1 P
+X ~ 4 250 0 100 L 30 30 4 1 P
+X ~ 5 250 0 100 L 30 30 5 1 P
+X ~ 6 250 0 100 L 30 30 6 1 P
+X ~ 7 250 0 100 L 30 30 7 1 P
+X ~ 8 250 0 100 L 30 30 8 1 P
+X ~ 9 250 0 100 L 30 30 9 1 P
+X ~ 10 250 0 100 L 30 30 10 1 P
+X ~ 11 250 0 100 L 30 30 11 1 P
+X ~ 12 250 0 100 L 30 30 12 1 P
+X ~ 13 250 0 100 L 30 30 13 1 P
+X ~ 14 250 0 100 L 30 30 14 1 P
+X ~ 15 250 0 100 L 30 30 15 1 P
+X ~ 16 250 0 100 L 30 30 16 1 P
+X ~ 17 250 0 100 L 30 30 17 1 P
+X ~ 18 250 0 100 L 30 30 18 1 P
+X ~ 19 250 0 100 L 30 30 19 1 P
+X ~ 20 250 0 100 L 30 30 20 1 P
+X ~ 21 250 0 100 L 30 30 21 1 P
+X ~ 22 250 0 100 L 30 30 22 1 P
+X ~ 23 250 0 100 L 30 30 23 1 P
+X ~ 24 250 0 100 L 30 30 24 1 P
+X ~ 25 250 0 100 L 30 30 25 1 P
+X ~ 26 250 0 100 L 30 30 26 1 P
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_buffer
+#
+DEF d_buffer U 0 40 Y Y 1 F N
+F0 "U" 0 -50 60 H V C CNN
+F1 "d_buffer" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N
+X IN 1 -500 0 200 R 50 50 1 1 I
+X OUT 2 650 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_tristate
+#
+DEF d_tristate U 0 40 Y Y 1 F N
+F0 "U" -250 250 60 H V C CNN
+F1 "d_tristate" -200 450 60 H V C CNN
+F2 "" -100 350 60 H V C CNN
+F3 "" -100 350 60 H V C CNN
+DRAW
+P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N
+X IN 1 -600 350 200 R 50 50 1 1 I
+X EN 2 -50 50 193 U 50 50 1 1 I
+X OUT 3 550 350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.cir b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.cir
new file mode 100644
index 00000000..3881f6bd
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.cir
@@ -0,0 +1,30 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74LVC257A\SN74LVC257A.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/10/25 11:05:59
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3  Net-_U1-Pad1_ Net-_U17-Pad2_ d_inverter		
+U4  Net-_U1-Pad2_ Net-_U11-Pad1_ d_inverter		
+U2  Net-_U1-Pad2_ Net-_U10-Pad1_ d_buffer		
+U5  Net-_U11-Pad1_ Net-_U1-Pad3_ Net-_U13-Pad1_ d_and		
+U6  Net-_U10-Pad1_ Net-_U1-Pad4_ Net-_U13-Pad2_ d_and		
+U7  Net-_U11-Pad1_ Net-_U1-Pad5_ Net-_U14-Pad1_ d_and		
+U8  Net-_U10-Pad1_ Net-_U1-Pad6_ Net-_U14-Pad2_ d_and		
+U9  Net-_U11-Pad1_ Net-_U1-Pad7_ Net-_U15-Pad1_ d_and		
+U10  Net-_U10-Pad1_ Net-_U1-Pad8_ Net-_U10-Pad3_ d_and		
+U11  Net-_U11-Pad1_ Net-_U1-Pad9_ Net-_U11-Pad3_ d_and		
+U12  Net-_U10-Pad1_ Net-_U1-Pad10_ Net-_U12-Pad3_ d_and		
+U13  Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_or		
+U14  Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_or		
+U15  Net-_U15-Pad1_ Net-_U10-Pad3_ Net-_U15-Pad3_ d_or		
+U16  Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U16-Pad3_ d_or		
+U17  Net-_U13-Pad3_ Net-_U17-Pad2_ Net-_U1-Pad11_ d_tristate		
+U18  Net-_U14-Pad3_ Net-_U17-Pad2_ Net-_U1-Pad12_ d_tristate		
+U19  Net-_U15-Pad3_ Net-_U17-Pad2_ Net-_U1-Pad13_ d_tristate		
+U20  Net-_U16-Pad3_ Net-_U17-Pad2_ Net-_U1-Pad14_ d_tristate		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.cir.out b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.cir.out
new file mode 100644
index 00000000..081abd5c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.cir.out
@@ -0,0 +1,88 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn74lvc257a\sn74lvc257a.cir
+
+* u3  net-_u1-pad1_ net-_u17-pad2_ d_inverter
+* u4  net-_u1-pad2_ net-_u11-pad1_ d_inverter
+* u2  net-_u1-pad2_ net-_u10-pad1_ d_buffer
+* u5  net-_u11-pad1_ net-_u1-pad3_ net-_u13-pad1_ d_and
+* u6  net-_u10-pad1_ net-_u1-pad4_ net-_u13-pad2_ d_and
+* u7  net-_u11-pad1_ net-_u1-pad5_ net-_u14-pad1_ d_and
+* u8  net-_u10-pad1_ net-_u1-pad6_ net-_u14-pad2_ d_and
+* u9  net-_u11-pad1_ net-_u1-pad7_ net-_u15-pad1_ d_and
+* u10  net-_u10-pad1_ net-_u1-pad8_ net-_u10-pad3_ d_and
+* u11  net-_u11-pad1_ net-_u1-pad9_ net-_u11-pad3_ d_and
+* u12  net-_u10-pad1_ net-_u1-pad10_ net-_u12-pad3_ d_and
+* u13  net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or
+* u14  net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_or
+* u15  net-_u15-pad1_ net-_u10-pad3_ net-_u15-pad3_ d_or
+* u16  net-_u11-pad3_ net-_u12-pad3_ net-_u16-pad3_ d_or
+* u17  net-_u13-pad3_ net-_u17-pad2_ net-_u1-pad11_ d_tristate
+* u18  net-_u14-pad3_ net-_u17-pad2_ net-_u1-pad12_ d_tristate
+* u19  net-_u15-pad3_ net-_u17-pad2_ net-_u1-pad13_ d_tristate
+* u20  net-_u16-pad3_ net-_u17-pad2_ net-_u1-pad14_ d_tristate
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
+a1 net-_u1-pad1_ net-_u17-pad2_ u3
+a2 net-_u1-pad2_ net-_u11-pad1_ u4
+a3 net-_u1-pad2_ net-_u10-pad1_ u2
+a4 [net-_u11-pad1_ net-_u1-pad3_ ] net-_u13-pad1_ u5
+a5 [net-_u10-pad1_ net-_u1-pad4_ ] net-_u13-pad2_ u6
+a6 [net-_u11-pad1_ net-_u1-pad5_ ] net-_u14-pad1_ u7
+a7 [net-_u10-pad1_ net-_u1-pad6_ ] net-_u14-pad2_ u8
+a8 [net-_u11-pad1_ net-_u1-pad7_ ] net-_u15-pad1_ u9
+a9 [net-_u10-pad1_ net-_u1-pad8_ ] net-_u10-pad3_ u10
+a10 [net-_u11-pad1_ net-_u1-pad9_ ] net-_u11-pad3_ u11
+a11 [net-_u10-pad1_ net-_u1-pad10_ ] net-_u12-pad3_ u12
+a12 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a13 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a14 [net-_u15-pad1_ net-_u10-pad3_ ] net-_u15-pad3_ u15
+a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u16-pad3_ u16
+a16 net-_u13-pad3_ net-_u17-pad2_ net-_u1-pad11_ u17
+a17 net-_u14-pad3_ net-_u17-pad2_ net-_u1-pad12_ u18
+a18 net-_u15-pad3_ net-_u17-pad2_ net-_u1-pad13_ u19
+a19 net-_u16-pad3_ net-_u17-pad2_ net-_u1-pad14_ u20
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_buffer, NgSpice Name: d_buffer
+.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u13 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
+.model u17 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
+* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
+.model u18 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
+* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
+.model u19 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
+* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
+.model u20 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.pro b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.sch b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.sch
new file mode 100644
index 00000000..5d0f9cf3
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.sch
@@ -0,0 +1,543 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_inverter U3
+U 1 1 681EE269
+P 2950 1375
+F 0 "U3" H 2950 1275 60  0000 C CNN
+F 1 "d_inverter" H 2950 1525 60  0000 C CNN
+F 2 "" H 3000 1325 60  0000 C CNN
+F 3 "" H 3000 1325 60  0000 C CNN
+	1    2950 1375
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 681EE2AE
+P 2950 1875
+F 0 "U4" H 2950 1775 60  0000 C CNN
+F 1 "d_inverter" H 2950 2025 60  0000 C CNN
+F 2 "" H 3000 1825 60  0000 C CNN
+F 3 "" H 3000 1825 60  0000 C CNN
+	1    2950 1875
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_buffer U2
+U 1 1 681EE2D0
+P 2350 2250
+F 0 "U2" H 2350 2200 60  0000 C CNN
+F 1 "d_buffer" H 2350 2300 60  0000 C CNN
+F 2 "" H 2350 2250 60  0000 C CNN
+F 3 "" H 2350 2250 60  0000 C CNN
+	1    2350 2250
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U5
+U 1 1 681EE388
+P 4125 2900
+F 0 "U5" H 4125 2900 60  0000 C CNN
+F 1 "d_and" H 4175 3000 60  0000 C CNN
+F 2 "" H 4125 2900 60  0000 C CNN
+F 3 "" H 4125 2900 60  0000 C CNN
+	1    4125 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U6
+U 1 1 681EE3BF
+P 4125 3300
+F 0 "U6" H 4125 3300 60  0000 C CNN
+F 1 "d_and" H 4175 3400 60  0000 C CNN
+F 2 "" H 4125 3300 60  0000 C CNN
+F 3 "" H 4125 3300 60  0000 C CNN
+	1    4125 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U7
+U 1 1 681EE3EC
+P 4125 3675
+F 0 "U7" H 4125 3675 60  0000 C CNN
+F 1 "d_and" H 4175 3775 60  0000 C CNN
+F 2 "" H 4125 3675 60  0000 C CNN
+F 3 "" H 4125 3675 60  0000 C CNN
+	1    4125 3675
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U8
+U 1 1 681EE513
+P 4125 4150
+F 0 "U8" H 4125 4150 60  0000 C CNN
+F 1 "d_and" H 4175 4250 60  0000 C CNN
+F 2 "" H 4125 4150 60  0000 C CNN
+F 3 "" H 4125 4150 60  0000 C CNN
+	1    4125 4150
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U9
+U 1 1 681EE519
+P 4125 4550
+F 0 "U9" H 4125 4550 60  0000 C CNN
+F 1 "d_and" H 4175 4650 60  0000 C CNN
+F 2 "" H 4125 4550 60  0000 C CNN
+F 3 "" H 4125 4550 60  0000 C CNN
+	1    4125 4550
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U10
+U 1 1 681EE51F
+P 4125 4925
+F 0 "U10" H 4125 4925 60  0000 C CNN
+F 1 "d_and" H 4175 5025 60  0000 C CNN
+F 2 "" H 4125 4925 60  0000 C CNN
+F 3 "" H 4125 4925 60  0000 C CNN
+	1    4125 4925
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U11
+U 1 1 681EE576
+P 4125 5275
+F 0 "U11" H 4125 5275 60  0000 C CNN
+F 1 "d_and" H 4175 5375 60  0000 C CNN
+F 2 "" H 4125 5275 60  0000 C CNN
+F 3 "" H 4125 5275 60  0000 C CNN
+	1    4125 5275
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U12
+U 1 1 681EE60E
+P 4125 5675
+F 0 "U12" H 4125 5675 60  0000 C CNN
+F 1 "d_and" H 4175 5775 60  0000 C CNN
+F 2 "" H 4125 5675 60  0000 C CNN
+F 3 "" H 4125 5675 60  0000 C CNN
+	1    4125 5675
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U13
+U 1 1 681EE688
+P 5250 3100
+F 0 "U13" H 5250 3100 60  0000 C CNN
+F 1 "d_or" H 5250 3200 60  0000 C CNN
+F 2 "" H 5250 3100 60  0000 C CNN
+F 3 "" H 5250 3100 60  0000 C CNN
+	1    5250 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U14
+U 1 1 681EE6D3
+P 5250 3925
+F 0 "U14" H 5250 3925 60  0000 C CNN
+F 1 "d_or" H 5250 4025 60  0000 C CNN
+F 2 "" H 5250 3925 60  0000 C CNN
+F 3 "" H 5250 3925 60  0000 C CNN
+	1    5250 3925
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U15
+U 1 1 681EE789
+P 5250 4700
+F 0 "U15" H 5250 4700 60  0000 C CNN
+F 1 "d_or" H 5250 4800 60  0000 C CNN
+F 2 "" H 5250 4700 60  0000 C CNN
+F 3 "" H 5250 4700 60  0000 C CNN
+	1    5250 4700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U16
+U 1 1 681EE813
+P 5250 5450
+F 0 "U16" H 5250 5450 60  0000 C CNN
+F 1 "d_or" H 5250 5550 60  0000 C CNN
+F 2 "" H 5250 5450 60  0000 C CNN
+F 3 "" H 5250 5450 60  0000 C CNN
+	1    5250 5450
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_tristate U17
+U 1 1 681EE8AC
+P 6600 2700
+F 0 "U17" H 6350 2950 60  0000 C CNN
+F 1 "d_tristate" H 6400 3150 60  0000 C CNN
+F 2 "" H 6500 3050 60  0000 C CNN
+F 3 "" H 6500 3050 60  0000 C CNN
+	1    6600 2700
+	1    0    0    1   
+$EndComp
+$Comp
+L d_tristate U18
+U 1 1 681EE982
+P 6600 3525
+F 0 "U18" H 6350 3775 60  0000 C CNN
+F 1 "d_tristate" H 6400 3975 60  0000 C CNN
+F 2 "" H 6500 3875 60  0000 C CNN
+F 3 "" H 6500 3875 60  0000 C CNN
+	1    6600 3525
+	1    0    0    1   
+$EndComp
+$Comp
+L d_tristate U19
+U 1 1 681EEAAC
+P 6600 4300
+F 0 "U19" H 6350 4550 60  0000 C CNN
+F 1 "d_tristate" H 6400 4750 60  0000 C CNN
+F 2 "" H 6500 4650 60  0000 C CNN
+F 3 "" H 6500 4650 60  0000 C CNN
+	1    6600 4300
+	1    0    0    1   
+$EndComp
+$Comp
+L d_tristate U20
+U 1 1 681EEB14
+P 6600 5050
+F 0 "U20" H 6350 5300 60  0000 C CNN
+F 1 "d_tristate" H 6400 5500 60  0000 C CNN
+F 2 "" H 6500 5400 60  0000 C CNN
+F 3 "" H 6500 5400 60  0000 C CNN
+	1    6600 5050
+	1    0    0    1   
+$EndComp
+Wire Wire Line
+	4575 2850 4575 3000
+Wire Wire Line
+	4575 3000 4800 3000
+Wire Wire Line
+	4800 3100 4575 3100
+Wire Wire Line
+	4575 3100 4575 3250
+Wire Wire Line
+	4575 3625 4575 3825
+Wire Wire Line
+	4575 3825 4800 3825
+Wire Wire Line
+	4800 3925 4575 3925
+Wire Wire Line
+	4575 3925 4575 4100
+Wire Wire Line
+	4575 4500 4575 4600
+Wire Wire Line
+	4575 4600 4800 4600
+Wire Wire Line
+	4800 4700 4575 4700
+Wire Wire Line
+	4575 4700 4575 4875
+Wire Wire Line
+	4575 5225 4575 5350
+Wire Wire Line
+	4575 5350 4800 5350
+Wire Wire Line
+	4800 5450 4575 5450
+Wire Wire Line
+	4575 5450 4575 5625
+Wire Wire Line
+	6000 5400 5700 5400
+Wire Wire Line
+	6000 4650 5700 4650
+Wire Wire Line
+	6000 3875 5700 3875
+Wire Wire Line
+	6000 3050 5700 3050
+Wire Wire Line
+	3250 1875 3475 1875
+Wire Wire Line
+	3475 1875 3475 5175
+Wire Wire Line
+	3475 5175 3675 5175
+Wire Wire Line
+	3675 3575 3475 3575
+Connection ~ 3475 3575
+Wire Wire Line
+	3675 2800 3475 2800
+Connection ~ 3475 2800
+Wire Wire Line
+	3675 4450 3475 4450
+Connection ~ 3475 4450
+Wire Wire Line
+	3000 2250 3100 2250
+Wire Wire Line
+	3100 2250 3100 5575
+Wire Wire Line
+	3100 5575 3675 5575
+Wire Wire Line
+	3675 4825 3100 4825
+Connection ~ 3100 4825
+Wire Wire Line
+	3675 4050 3100 4050
+Connection ~ 3100 4050
+Wire Wire Line
+	3675 3200 3100 3200
+Connection ~ 3100 3200
+Wire Wire Line
+	2425 2900 3675 2900
+Wire Wire Line
+	3675 3300 2425 3300
+Wire Wire Line
+	3675 3675 2425 3675
+Wire Wire Line
+	3675 4150 2425 4150
+Wire Wire Line
+	3675 4550 2425 4550
+Wire Wire Line
+	3675 5275 2425 5275
+Wire Wire Line
+	3675 5675 2425 5675
+Wire Wire Line
+	3250 1375 7375 1375
+Wire Wire Line
+	7375 1375 7375 5100
+Wire Wire Line
+	7375 5100 6550 5100
+Wire Wire Line
+	6550 4350 6550 4300
+Wire Wire Line
+	6550 4300 7375 4300
+Connection ~ 7375 4300
+Wire Wire Line
+	6550 3575 6550 3475
+Wire Wire Line
+	6550 3475 7375 3475
+Connection ~ 7375 3475
+Wire Wire Line
+	6550 2750 6550 2625
+Wire Wire Line
+	6550 2625 7375 2625
+Connection ~ 7375 2625
+Wire Wire Line
+	7150 3050 8075 3050
+Wire Wire Line
+	7150 3875 8075 3875
+Wire Wire Line
+	7150 4650 8075 4650
+Wire Wire Line
+	7150 5400 8075 5400
+Wire Wire Line
+	1375 1375 2650 1375
+Wire Wire Line
+	2650 1875 1375 1875
+Wire Wire Line
+	1850 2250 1675 2250
+Wire Wire Line
+	1675 2250 1675 1875
+Connection ~ 1675 1875
+$Comp
+L PORT U1
+U 1 1 681F1778
+P 1125 1375
+F 0 "U1" H 1175 1475 30  0000 C CNN
+F 1 "PORT" H 1125 1375 30  0000 C CNN
+F 2 "" H 1125 1375 60  0000 C CNN
+F 3 "" H 1125 1375 60  0000 C CNN
+	1    1125 1375
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 681F17BB
+P 1125 1875
+F 0 "U1" H 1175 1975 30  0000 C CNN
+F 1 "PORT" H 1125 1875 30  0000 C CNN
+F 2 "" H 1125 1875 60  0000 C CNN
+F 3 "" H 1125 1875 60  0000 C CNN
+	2    1125 1875
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 681F188F
+P 2175 2900
+F 0 "U1" H 2225 3000 30  0000 C CNN
+F 1 "PORT" H 2175 2900 30  0000 C CNN
+F 2 "" H 2175 2900 60  0000 C CNN
+F 3 "" H 2175 2900 60  0000 C CNN
+	3    2175 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 681F18D6
+P 2175 3300
+F 0 "U1" H 2225 3400 30  0000 C CNN
+F 1 "PORT" H 2175 3300 30  0000 C CNN
+F 2 "" H 2175 3300 60  0000 C CNN
+F 3 "" H 2175 3300 60  0000 C CNN
+	4    2175 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 681F19A9
+P 2175 3675
+F 0 "U1" H 2225 3775 30  0000 C CNN
+F 1 "PORT" H 2175 3675 30  0000 C CNN
+F 2 "" H 2175 3675 60  0000 C CNN
+F 3 "" H 2175 3675 60  0000 C CNN
+	5    2175 3675
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 681F19EE
+P 2175 4150
+F 0 "U1" H 2225 4250 30  0000 C CNN
+F 1 "PORT" H 2175 4150 30  0000 C CNN
+F 2 "" H 2175 4150 60  0000 C CNN
+F 3 "" H 2175 4150 60  0000 C CNN
+	6    2175 4150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 7 1 681F1AE8
+P 2175 4550
+F 0 "U1" H 2225 4650 30  0000 C CNN
+F 1 "PORT" H 2175 4550 30  0000 C CNN
+F 2 "" H 2175 4550 60  0000 C CNN
+F 3 "" H 2175 4550 60  0000 C CNN
+	7    2175 4550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 8 1 681F1B99
+P 2175 4925
+F 0 "U1" H 2225 5025 30  0000 C CNN
+F 1 "PORT" H 2175 4925 30  0000 C CNN
+F 2 "" H 2175 4925 60  0000 C CNN
+F 3 "" H 2175 4925 60  0000 C CNN
+	8    2175 4925
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2425 4925 3675 4925
+$Comp
+L PORT U1
+U 9 1 681F1EEC
+P 2175 5275
+F 0 "U1" H 2225 5375 30  0000 C CNN
+F 1 "PORT" H 2175 5275 30  0000 C CNN
+F 2 "" H 2175 5275 60  0000 C CNN
+F 3 "" H 2175 5275 60  0000 C CNN
+	9    2175 5275
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 10 1 681F1FD7
+P 2175 5675
+F 0 "U1" H 2225 5775 30  0000 C CNN
+F 1 "PORT" H 2175 5675 30  0000 C CNN
+F 2 "" H 2175 5675 60  0000 C CNN
+F 3 "" H 2175 5675 60  0000 C CNN
+	10   2175 5675
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 11 1 681F2150
+P 8325 3050
+F 0 "U1" H 8375 3150 30  0000 C CNN
+F 1 "PORT" H 8325 3050 30  0000 C CNN
+F 2 "" H 8325 3050 60  0000 C CNN
+F 3 "" H 8325 3050 60  0000 C CNN
+	11   8325 3050
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 12 1 681F21AD
+P 8325 3875
+F 0 "U1" H 8375 3975 30  0000 C CNN
+F 1 "PORT" H 8325 3875 30  0000 C CNN
+F 2 "" H 8325 3875 60  0000 C CNN
+F 3 "" H 8325 3875 60  0000 C CNN
+	12   8325 3875
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 13 1 681F2280
+P 8325 4650
+F 0 "U1" H 8375 4750 30  0000 C CNN
+F 1 "PORT" H 8325 4650 30  0000 C CNN
+F 2 "" H 8325 4650 60  0000 C CNN
+F 3 "" H 8325 4650 60  0000 C CNN
+	13   8325 4650
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 14 1 681F23B7
+P 8325 5400
+F 0 "U1" H 8375 5500 30  0000 C CNN
+F 1 "PORT" H 8325 5400 30  0000 C CNN
+F 2 "" H 8325 5400 60  0000 C CNN
+F 3 "" H 8325 5400 60  0000 C CNN
+	14   8325 5400
+	-1   0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.sub b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.sub
new file mode 100644
index 00000000..99057965
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.sub
@@ -0,0 +1,82 @@
+* Subcircuit SN74LVC257A
+.subckt SN74LVC257A net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ 
+* c:\fossee\esim\library\subcircuitlibrary\sn74lvc257a\sn74lvc257a.cir
+* u3  net-_u1-pad1_ net-_u17-pad2_ d_inverter
+* u4  net-_u1-pad2_ net-_u11-pad1_ d_inverter
+* u2  net-_u1-pad2_ net-_u10-pad1_ d_buffer
+* u5  net-_u11-pad1_ net-_u1-pad3_ net-_u13-pad1_ d_and
+* u6  net-_u10-pad1_ net-_u1-pad4_ net-_u13-pad2_ d_and
+* u7  net-_u11-pad1_ net-_u1-pad5_ net-_u14-pad1_ d_and
+* u8  net-_u10-pad1_ net-_u1-pad6_ net-_u14-pad2_ d_and
+* u9  net-_u11-pad1_ net-_u1-pad7_ net-_u15-pad1_ d_and
+* u10  net-_u10-pad1_ net-_u1-pad8_ net-_u10-pad3_ d_and
+* u11  net-_u11-pad1_ net-_u1-pad9_ net-_u11-pad3_ d_and
+* u12  net-_u10-pad1_ net-_u1-pad10_ net-_u12-pad3_ d_and
+* u13  net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or
+* u14  net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_or
+* u15  net-_u15-pad1_ net-_u10-pad3_ net-_u15-pad3_ d_or
+* u16  net-_u11-pad3_ net-_u12-pad3_ net-_u16-pad3_ d_or
+* u17  net-_u13-pad3_ net-_u17-pad2_ net-_u1-pad11_ d_tristate
+* u18  net-_u14-pad3_ net-_u17-pad2_ net-_u1-pad12_ d_tristate
+* u19  net-_u15-pad3_ net-_u17-pad2_ net-_u1-pad13_ d_tristate
+* u20  net-_u16-pad3_ net-_u17-pad2_ net-_u1-pad14_ d_tristate
+a1 net-_u1-pad1_ net-_u17-pad2_ u3
+a2 net-_u1-pad2_ net-_u11-pad1_ u4
+a3 net-_u1-pad2_ net-_u10-pad1_ u2
+a4 [net-_u11-pad1_ net-_u1-pad3_ ] net-_u13-pad1_ u5
+a5 [net-_u10-pad1_ net-_u1-pad4_ ] net-_u13-pad2_ u6
+a6 [net-_u11-pad1_ net-_u1-pad5_ ] net-_u14-pad1_ u7
+a7 [net-_u10-pad1_ net-_u1-pad6_ ] net-_u14-pad2_ u8
+a8 [net-_u11-pad1_ net-_u1-pad7_ ] net-_u15-pad1_ u9
+a9 [net-_u10-pad1_ net-_u1-pad8_ ] net-_u10-pad3_ u10
+a10 [net-_u11-pad1_ net-_u1-pad9_ ] net-_u11-pad3_ u11
+a11 [net-_u10-pad1_ net-_u1-pad10_ ] net-_u12-pad3_ u12
+a12 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a13 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a14 [net-_u15-pad1_ net-_u10-pad3_ ] net-_u15-pad3_ u15
+a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u16-pad3_ u16
+a16 net-_u13-pad3_ net-_u17-pad2_ net-_u1-pad11_ u17
+a17 net-_u14-pad3_ net-_u17-pad2_ net-_u1-pad12_ u18
+a18 net-_u15-pad3_ net-_u17-pad2_ net-_u1-pad13_ u19
+a19 net-_u16-pad3_ net-_u17-pad2_ net-_u1-pad14_ u20
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_buffer, NgSpice Name: d_buffer
+.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u13 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
+.model u17 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
+.model u18 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
+.model u19 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
+.model u20 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Control Statements
+
+.ends SN74LVC257A
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A_Previous_Values.xml b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A_Previous_Values.xml
new file mode 100644
index 00000000..62f4659b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u3 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u2 name="type">d_buffer<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u2><u5 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_and<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_or<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_or<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u14><u15 name="type">d_or<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u15><u16 name="type">d_or<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u16><u17 name="type">d_tristate<field46 name="Enter Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Enable Load (default=1.0e-12)" /></u17><u18 name="type">d_tristate<field49 name="Enter Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Enable Load (default=1.0e-12)" /></u18><u19 name="type">d_tristate<field52 name="Enter Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Enable Load (default=1.0e-12)" /></u19><u20 name="type">d_tristate<field55 name="Enter Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Enable Load (default=1.0e-12)" /></u20></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LVC257A/analysis b/library/SubcircuitLibrary/SN74LVC257A/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC257A/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file