Add TL431 adjustable shunt regulator subcircuit

13 files changed, 884 insertions, 0 deletions

diff --git a/library/SubcircuitLibrary/tl431/D.lib b/library/SubcircuitLibrary/tl431/D.lib
new file mode 100644
index 00000000..f53bf3e0
--- /dev/null
+++ b/library/SubcircuitLibrary/tl431/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/tl431/NPN.lib b/library/SubcircuitLibrary/tl431/NPN.lib
new file mode 100644
index 00000000..be5f3073
--- /dev/null
+++ b/library/SubcircuitLibrary/tl431/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p 
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/tl431/PNP.lib b/library/SubcircuitLibrary/tl431/PNP.lib
new file mode 100644
index 00000000..7edda0ea
--- /dev/null
+++ b/library/SubcircuitLibrary/tl431/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++		Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++		Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++		Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/library/SubcircuitLibrary/tl431/PowerDiode.lib b/library/SubcircuitLibrary/tl431/PowerDiode.lib
new file mode 100644
index 00000000..a2f61dce
--- /dev/null
+++ b/library/SubcircuitLibrary/tl431/PowerDiode.lib
@@ -0,0 +1,20 @@
+.MODEL PowerDiode D(
++ Vj=.75
++ Nbvl=14.976
++ Cjo=175p
++ Rs=.25
++ Isr=1.859n
++ Eg=1.11
++ M=.5516
++ Nbv=1.6989
++ N=1
++ Tbv1=-21.277u
++ bv=1800
++ Fc=.5
++ Ikf=0
++ Nr=2
++ Ibv=20.245m
++ Is=2.2E-15
++ Xti=3
++ Ibvl=1.9556m
+)
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/tl431/ZenerD1N750.lib b/library/SubcircuitLibrary/tl431/ZenerD1N750.lib
new file mode 100644
index 00000000..890c37fe
--- /dev/null
+++ b/library/SubcircuitLibrary/tl431/ZenerD1N750.lib
@@ -0,0 +1,3 @@
+.model D1N750	D( Is=880.5E-18 Rs=.25 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=175p M=.5516 
++ Vj=.75 Fc=.5 Isr=1.859n Nr=2 Bv=8.1 Ibv=20.245m Nbv=1.6989 Ibvl=1.9556m 
++ Nbvl=14.976 Tbv1=-21.277u) 
diff --git a/library/SubcircuitLibrary/tl431/analysis b/library/SubcircuitLibrary/tl431/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/tl431/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/tl431/tl431_sub-cache.lib b/library/SubcircuitLibrary/tl431/tl431_sub-cache.lib
new file mode 100644
index 00000000..155677e6
--- /dev/null
+++ b/library/SubcircuitLibrary/tl431/tl431_sub-cache.lib
@@ -0,0 +1,147 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 P
+X ~ 2 250 0 100 L 30 30 2 1 P
+X ~ 3 250 0 100 L 30 30 3 1 P
+X ~ 4 250 0 100 L 30 30 4 1 P
+X ~ 5 250 0 100 L 30 30 5 1 P
+X ~ 6 250 0 100 L 30 30 6 1 P
+X ~ 7 250 0 100 L 30 30 7 1 P
+X ~ 8 250 0 100 L 30 30 8 1 P
+X ~ 9 250 0 100 L 30 30 9 1 P
+X ~ 10 250 0 100 L 30 30 10 1 P
+X ~ 11 250 0 100 L 30 30 11 1 P
+X ~ 12 250 0 100 L 30 30 12 1 P
+X ~ 13 250 0 100 L 30 30 13 1 P
+X ~ 14 250 0 100 L 30 30 14 1 P
+X ~ 15 250 0 100 L 30 30 15 1 P
+X ~ 16 250 0 100 L 30 30 16 1 P
+X ~ 17 250 0 100 L 30 30 17 1 P
+X ~ 18 250 0 100 L 30 30 18 1 P
+X ~ 19 250 0 100 L 30 30 19 1 P
+X ~ 20 250 0 100 L 30 30 20 1 P
+X ~ 21 250 0 100 L 30 30 21 1 P
+X ~ 22 250 0 100 L 30 30 22 1 P
+X ~ 23 250 0 100 L 30 30 23 1 P
+X ~ 24 250 0 100 L 30 30 24 1 P
+X ~ 25 250 0 100 L 30 30 25 1 P
+X ~ 26 250 0 100 L 30 30 26 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_CP1
+#
+DEF eSim_CP1 C 0 10 N N 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_CP1" 25 -100 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS capacitor_polarised
+$FPLIST
+ CP_*
+$ENDFPLIST
+DRAW
+A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50
+P 2 0 1 20 -80 30 80 30 N
+P 2 0 1 0 -70 90 -30 90 N
+P 2 0 1 0 -50 70 -50 110 N
+X ~ 1 0 150 110 D 50 50 1 1 P
+X ~ 2 0 -150 130 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/tl431/tl431_sub.cir b/library/SubcircuitLibrary/tl431/tl431_sub.cir
new file mode 100644
index 00000000..d4a3caa4
--- /dev/null
+++ b/library/SubcircuitLibrary/tl431/tl431_sub.cir
@@ -0,0 +1,36 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\tl431_sub\tl431_sub.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/29/25 21:28:50
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q2  Net-_Q2-Pad1_ Net-_Q2-Pad1_ /Anode eSim_NPN		
+Q4  Net-_C1-Pad2_ Net-_Q2-Pad1_ Net-_Q4-Pad3_ eSim_NPN		
+Q9  Net-_C2-Pad2_ Net-_Q9-Pad2_ /Anode eSim_NPN		
+Q6  Net-_C1-Pad1_ Net-_C1-Pad2_ /Anode eSim_NPN		
+R1  Net-_R1-Pad1_ Net-_Q2-Pad1_ 2.4k		
+R3  Net-_R1-Pad1_ Net-_C1-Pad2_ 7.2k		
+R4  Net-_Q4-Pad3_ /Anode 800		
+R7  Net-_Q9-Pad2_ Net-_Q2-Pad1_ 1k		
+R6  Net-_Q5-Pad3_ Net-_C1-Pad1_ 4k		
+C1  Net-_C1-Pad1_ Net-_C1-Pad2_ 20p		
+Q5  Net-_Q5-Pad1_ Net-_Q1-Pad3_ Net-_Q5-Pad3_ eSim_NPN		
+R2  Net-_Q1-Pad3_ Net-_R1-Pad1_ 3.28k		
+Q1  /Cathode /Ref Net-_Q1-Pad3_ eSim_NPN		
+Q3  Net-_C2-Pad2_ Net-_C2-Pad2_ /Ref eSim_NPN		
+Q7  Net-_Q5-Pad1_ Net-_Q5-Pad1_ Net-_Q7-Pad3_ eSim_PNP		
+Q8  Net-_C2-Pad2_ Net-_Q5-Pad1_ Net-_Q8-Pad3_ eSim_PNP		
+R5  /Cathode Net-_Q7-Pad3_ 800		
+R8  /Cathode Net-_Q8-Pad3_ 800		
+D1  /Anode Net-_C2-Pad2_ eSim_Diode		
+C2  /Cathode Net-_C2-Pad2_ 20p		
+Q10  /Cathode Net-_C2-Pad2_ Net-_Q10-Pad3_ eSim_NPN		
+R9  Net-_Q10-Pad3_ Net-_Q11-Pad2_ 150		
+Q11  /Cathode Net-_Q11-Pad2_ /Anode eSim_NPN		
+R10  /Anode Net-_Q11-Pad2_ 10k		
+D2  /Anode /Cathode eSim_Diode		
+U1  /Cathode /Ref /Anode PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/tl431/tl431_sub.cir.out b/library/SubcircuitLibrary/tl431/tl431_sub.cir.out
new file mode 100644
index 00000000..40fed526
--- /dev/null
+++ b/library/SubcircuitLibrary/tl431/tl431_sub.cir.out
@@ -0,0 +1,40 @@
+* c:\fossee\esim\library\subcircuitlibrary\tl431_sub\tl431_sub.cir
+
+.include PNP.lib
+.include NPN.lib
+.include D.lib
+q2 net-_q2-pad1_ net-_q2-pad1_ /anode Q2N2222
+q4 net-_c1-pad2_ net-_q2-pad1_ net-_q4-pad3_ Q2N2222
+q9 net-_c2-pad2_ net-_q9-pad2_ /anode Q2N2222
+q6 net-_c1-pad1_ net-_c1-pad2_ /anode Q2N2222
+r1  net-_r1-pad1_ net-_q2-pad1_ 2.4k
+r3  net-_r1-pad1_ net-_c1-pad2_ 7.2k
+r4  net-_q4-pad3_ /anode 800
+r7  net-_q9-pad2_ net-_q2-pad1_ 1k
+r6  net-_q5-pad3_ net-_c1-pad1_ 4k
+c1  net-_c1-pad1_ net-_c1-pad2_ 20p
+q5 net-_q5-pad1_ net-_q1-pad3_ net-_q5-pad3_ Q2N2222
+r2  net-_q1-pad3_ net-_r1-pad1_ 3.28k
+q1 /cathode /ref net-_q1-pad3_ Q2N2222
+q3 net-_c2-pad2_ net-_c2-pad2_ /ref Q2N2222
+q7 net-_q5-pad1_ net-_q5-pad1_ net-_q7-pad3_ Q2N2907A
+q8 net-_c2-pad2_ net-_q5-pad1_ net-_q8-pad3_ Q2N2907A
+r5  /cathode net-_q7-pad3_ 800
+r8  /cathode net-_q8-pad3_ 800
+d1 /anode net-_c2-pad2_ 1N4148
+c2  /cathode net-_c2-pad2_ 20p
+q10 /cathode net-_c2-pad2_ net-_q10-pad3_ Q2N2222
+r9  net-_q10-pad3_ net-_q11-pad2_ 150
+q11 /cathode net-_q11-pad2_ /anode Q2N2222
+r10  /anode net-_q11-pad2_ 10k
+d2 /anode /cathode 1N4148
+* u1  /cathode /ref /anode port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/tl431/tl431_sub.pro b/library/SubcircuitLibrary/tl431/tl431_sub.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/tl431/tl431_sub.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/tl431/tl431_sub.sch b/library/SubcircuitLibrary/tl431/tl431_sub.sch
new file mode 100644
index 00000000..9c921954
--- /dev/null
+++ b/library/SubcircuitLibrary/tl431/tl431_sub.sch
@@ -0,0 +1,519 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:tl431_sub-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_NPN Q2
+U 1 1 67E78EB3
+P 3500 5250
+F 0 "Q2" H 3400 5300 50  0000 R CNN
+F 1 "eSim_NPN" H 3450 5400 50  0000 R CNN
+F 2 "" H 3700 5350 29  0000 C CNN
+F 3 "" H 3500 5250 60  0000 C CNN
+	1    3500 5250
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q4
+U 1 1 67E78EB4
+P 4850 5250
+F 0 "Q4" H 4750 5300 50  0000 R CNN
+F 1 "eSim_NPN" H 4800 5400 50  0000 R CNN
+F 2 "" H 5050 5350 29  0000 C CNN
+F 3 "" H 4850 5250 60  0000 C CNN
+	1    4850 5250
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q9
+U 1 1 67E78EB5
+P 7200 5650
+F 0 "Q9" H 7100 5700 50  0000 R CNN
+F 1 "eSim_NPN" H 7150 5800 50  0000 R CNN
+F 2 "" H 7400 5750 29  0000 C CNN
+F 3 "" H 7200 5650 60  0000 C CNN
+	1    7200 5650
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q6
+U 1 1 67E78EB6
+P 6000 4900
+F 0 "Q6" H 5900 4950 50  0000 R CNN
+F 1 "eSim_NPN" H 5950 5050 50  0000 R CNN
+F 2 "" H 6200 5000 29  0000 C CNN
+F 3 "" H 6000 4900 60  0000 C CNN
+	1    6000 4900
+	1    0    0    -1  
+$EndComp
+$Comp
+L resistor R1
+U 1 1 67E78EB7
+P 3450 4550
+F 0 "R1" H 3500 4680 50  0000 C CNN
+F 1 "2.4k" H 3500 4500 50  0000 C CNN
+F 2 "" H 3500 4530 30  0000 C CNN
+F 3 "" V 3500 4600 30  0000 C CNN
+	1    3450 4550
+	0    -1   1    0   
+$EndComp
+$Comp
+L resistor R3
+U 1 1 67E78EB8
+P 5000 4550
+F 0 "R3" H 5050 4680 50  0000 C CNN
+F 1 "7.2k" H 5050 4500 50  0000 C CNN
+F 2 "" H 5050 4530 30  0000 C CNN
+F 3 "" V 5050 4600 30  0000 C CNN
+	1    5000 4550
+	0    -1   1    0   
+$EndComp
+$Comp
+L resistor R4
+U 1 1 67E78EB9
+P 5000 5900
+F 0 "R4" H 5050 6030 50  0000 C CNN
+F 1 "800" H 5050 5850 50  0000 C CNN
+F 2 "" H 5050 5880 30  0000 C CNN
+F 3 "" V 5050 5950 30  0000 C CNN
+	1    5000 5900
+	0    -1   1    0   
+$EndComp
+$Comp
+L resistor R7
+U 1 1 67E78EBA
+P 6550 5700
+F 0 "R7" H 6600 5830 50  0000 C CNN
+F 1 "1k" H 6600 5650 50  0000 C CNN
+F 2 "" H 6600 5680 30  0000 C CNN
+F 3 "" V 6600 5750 30  0000 C CNN
+	1    6550 5700
+	-1   0    0    -1  
+$EndComp
+Wire Wire Line
+	3400 4750 3400 5050
+Wire Wire Line
+	4950 4750 4950 5050
+Wire Wire Line
+	3700 5250 4650 5250
+Wire Wire Line
+	4950 5450 4950 5800
+Wire Wire Line
+	6650 5650 7000 5650
+Wire Wire Line
+	3400 4900 4000 4900
+Wire Wire Line
+	4000 4900 4000 5250
+Connection ~ 4000 5250
+Connection ~ 3400 4900
+Wire Wire Line
+	4300 5650 4300 5250
+Connection ~ 4300 5250
+Wire Wire Line
+	3400 4450 3400 4200
+Wire Wire Line
+	3400 4200 4950 4200
+Wire Wire Line
+	4950 4200 4950 4450
+Wire Wire Line
+	4950 4900 5800 4900
+Connection ~ 4950 4900
+$Comp
+L resistor R6
+U 1 1 67E78EBB
+P 6150 4300
+F 0 "R6" H 6200 4430 50  0000 C CNN
+F 1 "4k" H 6200 4250 50  0000 C CNN
+F 2 "" H 6200 4280 30  0000 C CNN
+F 3 "" V 6200 4350 30  0000 C CNN
+	1    6150 4300
+	0    -1   1    0   
+$EndComp
+Wire Wire Line
+	6100 4500 6100 4700
+$Comp
+L capacitor_polarised C1
+U 1 1 67E78EBC
+P 5450 4700
+F 0 "C1" H 5475 4800 50  0000 L CNN
+F 1 "20p" H 5475 4600 50  0000 L CNN
+F 2 "" H 5450 4700 50  0001 C CNN
+F 3 "" H 5450 4700 50  0001 C CNN
+	1    5450 4700
+	-1   0    0    -1  
+$EndComp
+Wire Wire Line
+	5450 4550 6100 4550
+Connection ~ 6100 4550
+Wire Wire Line
+	5450 4850 5450 4900
+Connection ~ 5450 4900
+$Comp
+L eSim_NPN Q5
+U 1 1 67E78EBD
+P 6000 3800
+F 0 "Q5" H 5900 3850 50  0000 R CNN
+F 1 "eSim_NPN" H 5950 3950 50  0000 R CNN
+F 2 "" H 6200 3900 29  0000 C CNN
+F 3 "" H 6000 3800 60  0000 C CNN
+	1    6000 3800
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6100 4200 6100 4000
+$Comp
+L resistor R2
+U 1 1 67E78EBE
+P 4100 3950
+F 0 "R2" H 4150 4080 50  0000 C CNN
+F 1 "3.28k" H 4150 3900 50  0000 C CNN
+F 2 "" H 4150 3930 30  0000 C CNN
+F 3 "" V 4150 4000 30  0000 C CNN
+	1    4100 3950
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	4150 4150 4150 4200
+Connection ~ 4150 4200
+$Comp
+L eSim_NPN Q1
+U 1 1 67E78EBF
+P 3500 3000
+F 0 "Q1" H 3400 3050 50  0000 R CNN
+F 1 "eSim_NPN" H 3450 3150 50  0000 R CNN
+F 2 "" H 3700 3100 29  0000 C CNN
+F 3 "" H 3500 3000 60  0000 C CNN
+	1    3500 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q3
+U 1 1 67E78EC0
+P 4450 3100
+F 0 "Q3" H 4350 3150 50  0000 R CNN
+F 1 "eSim_NPN" H 4400 3250 50  0000 R CNN
+F 2 "" H 4650 3200 29  0000 C CNN
+F 3 "" H 4450 3100 60  0000 C CNN
+	1    4450 3100
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_PNP Q7
+U 1 1 67E78EC1
+P 6200 2650
+F 0 "Q7" H 6100 2700 50  0000 R CNN
+F 1 "eSim_PNP" H 6150 2800 50  0000 R CNN
+F 2 "" H 6400 2750 29  0000 C CNN
+F 3 "" H 6200 2650 60  0000 C CNN
+	1    6200 2650
+	-1   0    0    1   
+$EndComp
+$Comp
+L eSim_PNP Q8
+U 1 1 67E78EC2
+P 7200 2650
+F 0 "Q8" H 7100 2700 50  0000 R CNN
+F 1 "eSim_PNP" H 7150 2800 50  0000 R CNN
+F 2 "" H 7400 2750 29  0000 C CNN
+F 3 "" H 7200 2650 60  0000 C CNN
+	1    7200 2650
+	1    0    0    1   
+$EndComp
+$Comp
+L resistor R5
+U 1 1 67E78EC3
+P 6050 2050
+F 0 "R5" H 6100 2180 50  0000 C CNN
+F 1 "800" H 6100 2000 50  0000 C CNN
+F 2 "" H 6100 2030 30  0000 C CNN
+F 3 "" V 6100 2100 30  0000 C CNN
+	1    6050 2050
+	0    1    1    0   
+$EndComp
+$Comp
+L resistor R8
+U 1 1 67E78EC4
+P 7250 2100
+F 0 "R8" H 7300 2230 50  0000 C CNN
+F 1 "800" H 7300 2050 50  0000 C CNN
+F 2 "" H 7300 2080 30  0000 C CNN
+F 3 "" V 7300 2150 30  0000 C CNN
+	1    7250 2100
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	3600 3200 3600 3800
+Wire Wire Line
+	6100 2450 6100 2250
+Wire Wire Line
+	7300 2450 7300 2300
+Wire Wire Line
+	6100 2850 6100 3600
+Wire Wire Line
+	6400 2650 7000 2650
+Wire Wire Line
+	6700 2650 6700 2950
+Wire Wire Line
+	6700 2950 6100 2950
+Connection ~ 6100 2950
+Connection ~ 6700 2650
+Wire Wire Line
+	7300 2850 7300 5450
+Wire Wire Line
+	4650 3200 7300 3200
+Connection ~ 7300 3200
+Wire Wire Line
+	4450 2900 4450 2600
+Wire Wire Line
+	4450 2600 5050 2600
+Wire Wire Line
+	5050 2600 5050 3200
+Connection ~ 5050 3200
+$Comp
+L eSim_Diode D1
+U 1 1 67E78EC5
+P 7600 4400
+F 0 "D1" H 7600 4500 50  0000 C CNN
+F 1 "eSim_Diode" H 7600 4300 50  0000 C CNN
+F 2 "" H 7600 4400 60  0000 C CNN
+F 3 "" H 7600 4400 60  0000 C CNN
+	1    7600 4400
+	0    1    -1   0   
+$EndComp
+$Comp
+L capacitor_polarised C2
+U 1 1 67E78EC6
+P 7700 2500
+F 0 "C2" H 7725 2600 50  0000 L CNN
+F 1 "20p" H 7725 2400 50  0000 L CNN
+F 2 "" H 7700 2500 50  0001 C CNN
+F 3 "" H 7700 2500 50  0001 C CNN
+	1    7700 2500
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q10
+U 1 1 67E78EC7
+P 8400 3600
+F 0 "Q10" H 8300 3650 50  0000 R CNN
+F 1 "eSim_NPN" H 8350 3750 50  0000 R CNN
+F 2 "" H 8600 3700 29  0000 C CNN
+F 3 "" H 8400 3600 60  0000 C CNN
+	1    8400 3600
+	1    0    0    -1  
+$EndComp
+$Comp
+L resistor R9
+U 1 1 67E78EC8
+P 8850 3850
+F 0 "R9" H 8900 3980 50  0000 C CNN
+F 1 "150" H 8900 3800 50  0000 C CNN
+F 2 "" H 8900 3830 30  0000 C CNN
+F 3 "" V 8900 3900 30  0000 C CNN
+	1    8850 3850
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q11
+U 1 1 67E78EC9
+P 9600 3800
+F 0 "Q11" H 9500 3850 50  0000 R CNN
+F 1 "eSim_NPN" H 9550 3950 50  0000 R CNN
+F 2 "" H 9800 3900 29  0000 C CNN
+F 3 "" H 9600 3800 60  0000 C CNN
+	1    9600 3800
+	1    0    0    -1  
+$EndComp
+$Comp
+L resistor R10
+U 1 1 67E78ECA
+P 9200 4300
+F 0 "R10" H 9250 4430 50  0000 C CNN
+F 1 "10k" H 9250 4250 50  0000 C CNN
+F 2 "" H 9250 4280 30  0000 C CNN
+F 3 "" V 9250 4350 30  0000 C CNN
+	1    9200 4300
+	0    1    -1   0   
+$EndComp
+$Comp
+L eSim_Diode D2
+U 1 1 67E78ECB
+P 10100 4350
+F 0 "D2" H 10100 4450 50  0000 C CNN
+F 1 "eSim_Diode" H 10100 4250 50  0000 C CNN
+F 2 "" H 10100 4350 60  0000 C CNN
+F 3 "" H 10100 4350 60  0000 C CNN
+	1    10100 4350
+	0    1    -1   0   
+$EndComp
+Wire Wire Line
+	7300 3600 8200 3600
+Connection ~ 7300 3600
+Wire Wire Line
+	7700 2650 7700 3600
+Connection ~ 7700 3600
+Wire Wire Line
+	7600 4250 7600 3600
+Connection ~ 7600 3600
+Wire Wire Line
+	6350 5650 4300 5650
+Wire Wire Line
+	8500 3800 8750 3800
+Wire Wire Line
+	9050 3800 9400 3800
+Wire Wire Line
+	9250 4100 9250 3800
+Connection ~ 9250 3800
+Wire Wire Line
+	10100 6200 10100 4500
+Wire Wire Line
+	2650 6200 10100 6200
+Wire Wire Line
+	3400 5450 3400 6200
+Connection ~ 3400 6200
+Wire Wire Line
+	4950 6100 4950 6200
+Connection ~ 4950 6200
+Wire Wire Line
+	7300 5850 7300 6200
+Connection ~ 7300 6200
+Wire Wire Line
+	7600 4550 7600 6200
+Connection ~ 7600 6200
+Wire Wire Line
+	9700 4000 9700 6200
+Connection ~ 9700 6200
+Wire Wire Line
+	9250 4400 9250 4550
+Wire Wire Line
+	9250 4550 9700 4550
+Connection ~ 9700 4550
+Wire Wire Line
+	9700 1800 9700 3600
+Wire Wire Line
+	2200 1800 10100 1800
+Wire Wire Line
+	3600 2800 3600 1800
+Connection ~ 3600 1800
+Wire Wire Line
+	6100 1950 6100 1800
+Connection ~ 6100 1800
+Wire Wire Line
+	7300 2000 7300 1800
+Connection ~ 7300 1800
+Wire Wire Line
+	7700 2350 7700 1800
+Connection ~ 7700 1800
+Wire Wire Line
+	8500 3400 8500 1800
+Connection ~ 8500 1800
+Wire Wire Line
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+Connection ~ 9700 1800
+Wire Wire Line
+	3600 3800 5800 3800
+Wire Wire Line
+	4150 3850 4150 3800
+Connection ~ 4150 3800
+Wire Wire Line
+	6100 5100 6100 6200
+Connection ~ 6100 6200
+$Comp
+L PORT U1
+U 1 1 67E78ECC
+P 1950 1800
+F 0 "U1" H 2000 1900 30  0000 C CNN
+F 1 "PORT" H 1950 1800 30  0000 C CNN
+F 2 "" H 1950 1800 60  0000 C CNN
+F 3 "" H 1950 1800 60  0000 C CNN
+	1    1950 1800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 67E78ECD
+P 2400 3000
+F 0 "U1" H 2450 3100 30  0000 C CNN
+F 1 "PORT" H 2400 3000 30  0000 C CNN
+F 2 "" H 2400 3000 60  0000 C CNN
+F 3 "" H 2400 3000 60  0000 C CNN
+	2    2400 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 67E78ECE
+P 2400 6200
+F 0 "U1" H 2450 6300 30  0000 C CNN
+F 1 "PORT" H 2400 6200 30  0000 C CNN
+F 2 "" H 2400 6200 60  0000 C CNN
+F 3 "" H 2400 6200 60  0000 C CNN
+	3    2400 6200
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2650 3000 3300 3000
+Wire Wire Line
+	4250 3200 2975 3200
+Wire Wire Line
+	2975 3200 2975 3000
+Connection ~ 2975 3000
+Text Label 2330 1800 0    60   ~ 0
+Cathode
+Text Label 2710 3000 0    60   ~ 0
+Ref
+Text Label 2850 6200 0    60   ~ 0
+Anode
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/tl431/tl431_sub.sub b/library/SubcircuitLibrary/tl431/tl431_sub.sub
new file mode 100644
index 00000000..f26748b7
--- /dev/null
+++ b/library/SubcircuitLibrary/tl431/tl431_sub.sub
@@ -0,0 +1,34 @@
+* Subcircuit tl431_sub
+.subckt tl431_sub /cathode /ref /anode 
+* c:\fossee\esim\library\subcircuitlibrary\tl431_sub\tl431_sub.cir
+.include PNP.lib
+.include NPN.lib
+.include D.lib
+q2 net-_q2-pad1_ net-_q2-pad1_ /anode Q2N2222
+q4 net-_c1-pad2_ net-_q2-pad1_ net-_q4-pad3_ Q2N2222
+q9 net-_c2-pad2_ net-_q9-pad2_ /anode Q2N2222
+q6 net-_c1-pad1_ net-_c1-pad2_ /anode Q2N2222
+r1  net-_r1-pad1_ net-_q2-pad1_ 2.4k
+r3  net-_r1-pad1_ net-_c1-pad2_ 7.2k
+r4  net-_q4-pad3_ /anode 800
+r7  net-_q9-pad2_ net-_q2-pad1_ 1k
+r6  net-_q5-pad3_ net-_c1-pad1_ 4k
+c1  net-_c1-pad1_ net-_c1-pad2_ 20p
+q5 net-_q5-pad1_ net-_q1-pad3_ net-_q5-pad3_ Q2N2222
+r2  net-_q1-pad3_ net-_r1-pad1_ 3.28k
+q1 /cathode /ref net-_q1-pad3_ Q2N2222
+q3 net-_c2-pad2_ net-_c2-pad2_ /ref Q2N2222
+q7 net-_q5-pad1_ net-_q5-pad1_ net-_q7-pad3_ Q2N2907A
+q8 net-_c2-pad2_ net-_q5-pad1_ net-_q8-pad3_ Q2N2907A
+r5  /cathode net-_q7-pad3_ 800
+r8  /cathode net-_q8-pad3_ 800
+d1 /anode net-_c2-pad2_ 1N4148
+c2  /cathode net-_c2-pad2_ 20p
+q10 /cathode net-_c2-pad2_ net-_q10-pad3_ Q2N2222
+r9  net-_q10-pad3_ net-_q11-pad2_ 150
+q11 /cathode net-_q11-pad2_ /anode Q2N2222
+r10  /anode net-_q11-pad2_ 10k
+d2 /anode /cathode 1N4148
+* Control Statements
+
+.ends tl431_sub
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/tl431/tl431_sub_Previous_Values.xml b/library/SubcircuitLibrary/tl431/tl431_sub_Previous_Values.xml
new file mode 100644
index 00000000..4de18244
--- /dev/null
+++ b/library/SubcircuitLibrary/tl431/tl431_sub_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model /><devicemodel><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file