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| author | GanderlaChaithanya | 2025-06-30 12:29:03 +0530 |
|---|---|---|
| committer | GanderlaChaithanya | 2025-06-30 12:29:03 +0530 |
| commit | 19af40fa72cdc7589ca47d692a7e397b871dc467 (patch) | |
| tree | 942e8f3352d92a1f9fccfd338e451e7f36dddb22 | |
| parent | d1e62cdd6018db1c12044208775acc405b56c46b (diff) | |
| download | eSim-19af40fa72cdc7589ca47d692a7e397b871dc467.tar.gz eSim-19af40fa72cdc7589ca47d692a7e397b871dc467.tar.bz2 eSim-19af40fa72cdc7589ca47d692a7e397b871dc467.zip | |
Verilog Code for TriState Buffer for the SubCircuit - SN54ALS29827
| -rw-r--r-- | library/SubcircuitLibrary/sn54als29827/tristate_buff.v | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/sn54als29827/tristate_buff.v b/library/SubcircuitLibrary/sn54als29827/tristate_buff.v new file mode 100644 index 00000000..3f3863a7 --- /dev/null +++ b/library/SubcircuitLibrary/sn54als29827/tristate_buff.v @@ -0,0 +1,3 @@ +module tristate_buff(input wire a, input wire enable, output wire y); +assign y = (enable) ? a : 1'bz; +endmodule
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