D Flip Flop Verilog Code for SubCircuit - Bidirectional Shift Register

1 files changed, 12 insertions, 0 deletions

diff --git a/library/SubcircuitLibrary/bidirectional_shift_reg/dff_rst.v b/library/SubcircuitLibrary/bidirectional_shift_reg/dff_rst.v
new file mode 100644
index 00000000..da896fa8
--- /dev/null
+++ b/library/SubcircuitLibrary/bidirectional_shift_reg/dff_rst.v
@@ -0,0 +1,12 @@
+module dff_rst(d,rst,clk,q);
+input d,clk,rst;
+output reg q;
+always @(posedge clk) begin
+if(rst) begin
+q<=1'b0;
+end
+else begin
+q<=d;
+end
+end
+endmodule
\ No newline at end of file