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authorprashant2015-09-24 12:23:41 +0530
committerprashant2015-09-24 12:23:41 +0530
commit058634843b44a2cf695c77fcb7d30d6feb2a9e12 (patch)
treeaae29dc64c21cadaef54bf495f4fae342ef9d916 /pdf/1/1 FWR
parentba081ebbf3bccd0c6d8aa98798fc5c396bea0f48 (diff)
downloadscilab_textbook_companion-058634843b44a2cf695c77fcb7d30d6feb2a9e12.tar.gz
scilab_textbook_companion-058634843b44a2cf695c77fcb7d30d6feb2a9e12.tar.bz2
scilab_textbook_companion-058634843b44a2cf695c77fcb7d30d6feb2a9e12.zip
module updated to Drupal 7
Diffstat (limited to 'pdf/1/1 FWR')
-rwxr-xr-xpdf/1/1 FWR/FWR-cache.bak99
-rwxr-xr-xpdf/1/1 FWR/FWR-cache.lib125
-rwxr-xr-xpdf/1/1 FWR/FWR.bak204
-rwxr-xr-xpdf/1/1 FWR/FWR.cir16
-rwxr-xr-xpdf/1/1 FWR/FWR.cir.ckt14
-rwxr-xr-xpdf/1/1 FWR/FWR.cir.out21
-rwxr-xr-xpdf/1/1 FWR/FWR.pro74
-rwxr-xr-xpdf/1/1 FWR/FWR.proj1
-rwxr-xr-xpdf/1/1 FWR/FWR.sch199
-rwxr-xr-xpdf/1/1 FWR/FWR_last_input.txt1
-rwxr-xr-xpdf/1/1 FWR/analysis1
-rwxr-xr-xpdf/1/1 FWR/eeschema.exebin0 -> 6768128 bytes
-rwxr-xr-xpdf/1/1 FWR/libfftw3-3.dllbin0 -> 2365756 bytes
-rwxr-xr-xpdf/1/1 FWR/ngspice.exebin0 -> 4744192 bytes
-rwxr-xr-xpdf/1/1 FWR/plot_data_i.txt116
-rwxr-xr-xpdf/1/1 FWR/plot_data_v.txt116
-rwxr-xr-xpdf/1/1 FWR/python.exebin0 -> 26624 bytes
-rwxr-xr-xpdf/1/1 FWR/vcomp100.dllbin0 -> 51024 bytes
18 files changed, 987 insertions, 0 deletions
diff --git a/pdf/1/1 FWR/FWR-cache.bak b/pdf/1/1 FWR/FWR-cache.bak
new file mode 100755
index 0000000..9b33bd3
--- /dev/null
+++ b/pdf/1/1 FWR/FWR-cache.bak
@@ -0,0 +1,99 @@
+EESchema-LIBRARY Version 2.3 Date: 12/15/2014 3:57:40 PM
+#encoding utf-8
+#
+# DIODE
+#
+DEF DIODE D 0 40 N N 1 F N
+F0 "D" 0 100 40 H V C CNN
+F1 "DIODE" 0 -100 40 H V C CNN
+$FPLIST
+ D?
+ S*
+$ENDFPLIST
+DRAW
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -200 0 150 R 40 40 1 1 P
+X K 2 200 0 150 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0 0 0 0 100 0 100 N
+P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+ SM1206
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+# vplot8_1
+#
+DEF vplot8_1 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8_1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+X + 2 0 -300 200 U 40 40 2 1 I
+X + 3 0 -300 200 U 40 40 3 1 I
+X + 4 0 -300 200 U 40 40 4 1 I
+X + 5 0 -300 200 U 40 40 5 1 I
+X + 6 0 -300 200 U 40 40 6 1 I
+X + 7 0 -300 200 U 40 40 7 1 I
+X + 8 0 -300 200 U 40 40 8 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/pdf/1/1 FWR/FWR-cache.lib b/pdf/1/1 FWR/FWR-cache.lib
new file mode 100755
index 0000000..1e3b489
--- /dev/null
+++ b/pdf/1/1 FWR/FWR-cache.lib
@@ -0,0 +1,125 @@
+EESchema-LIBRARY Version 2.3 Date: 12/15/2014 4:18:40 PM
+#encoding utf-8
+#
+# DIODE
+#
+DEF DIODE D 0 40 N N 1 F N
+F0 "D" 0 100 40 H V C CNN
+F1 "DIODE" 0 -100 40 H V C CNN
+$FPLIST
+ D?
+ S*
+$ENDFPLIST
+DRAW
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -200 0 150 R 40 40 1 1 P
+X K 2 200 0 150 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0 0 0 0 100 0 100 N
+P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+ SM1206
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+# vplot8
+#
+DEF vplot8 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 -300 0 200 R 40 40 1 1 O
+X - 9 300 0 200 L 40 40 1 1 O
+X + 2 -300 0 200 R 40 40 2 1 O
+X - 10 300 0 200 L 40 40 2 1 O
+X + 3 -300 0 200 R 40 40 3 1 O
+X - 11 300 0 200 L 40 40 3 1 O
+X + 4 -300 0 200 R 40 40 4 1 O
+X - 12 300 0 200 L 40 40 4 1 O
+X + 5 -300 0 200 R 40 40 5 1 O
+X - 13 300 0 200 L 40 40 5 1 O
+X + 6 -300 0 200 R 40 40 6 1 O
+X - 14 300 0 200 L 40 40 6 1 O
+X + 7 -300 0 200 R 40 40 7 1 O
+X - 15 300 0 200 L 40 40 7 1 O
+X + 8 -300 0 200 R 40 40 8 1 O
+X - 16 300 0 200 L 40 40 8 1 O
+ENDDRAW
+ENDDEF
+#
+# vplot8_1
+#
+DEF vplot8_1 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8_1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+X + 2 0 -300 200 U 40 40 2 1 I
+X + 3 0 -300 200 U 40 40 3 1 I
+X + 4 0 -300 200 U 40 40 4 1 I
+X + 5 0 -300 200 U 40 40 5 1 I
+X + 6 0 -300 200 U 40 40 6 1 I
+X + 7 0 -300 200 U 40 40 7 1 I
+X + 8 0 -300 200 U 40 40 8 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/pdf/1/1 FWR/FWR.bak b/pdf/1/1 FWR/FWR.bak
new file mode 100755
index 0000000..258bcc6
--- /dev/null
+++ b/pdf/1/1 FWR/FWR.bak
@@ -0,0 +1,204 @@
+EESchema Schematic File Version 2 date 12/15/2014 3:57:40 PM
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+EELAYER 43 0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "15 dec 2014"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L VPLOT8_1 U?
+U 1 1 548EB795
+P 3550 4850
+F 0 "U?" H 3400 4950 50 0000 C CNN
+F 1 "VPLOT8_1" H 3700 4950 50 0000 C CNN
+ 1 3550 4850
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1400 4600 1400 5250
+Connection ~ 3550 5150
+Connection ~ 1550 4850
+Wire Wire Line
+ 4650 4950 4650 5150
+Wire Wire Line
+ 4650 5150 1700 5150
+Wire Wire Line
+ 1400 3700 1400 3450
+Wire Wire Line
+ 1400 3450 2850 3450
+Connection ~ 3650 4100
+Wire Wire Line
+ 3650 4100 4650 4100
+Connection ~ 2850 3900
+Wire Wire Line
+ 2850 3450 2850 3900
+Wire Wire Line
+ 2600 4400 3100 4400
+Wire Wire Line
+ 3500 4400 3650 4400
+Wire Wire Line
+ 3650 4400 3650 3900
+Wire Wire Line
+ 3650 3900 3500 3900
+Wire Wire Line
+ 2600 3900 3100 3900
+Wire Wire Line
+ 2200 3900 2000 3900
+Wire Wire Line
+ 2000 3900 2000 4400
+Wire Wire Line
+ 2000 4400 2200 4400
+Wire Wire Line
+ 2850 4400 2850 4850
+Connection ~ 2850 4400
+Wire Wire Line
+ 2850 4850 1400 4850
+Wire Wire Line
+ 2000 4150 1700 4150
+Connection ~ 2000 4150
+Wire Wire Line
+ 1700 4150 1700 5150
+Wire Wire Line
+ 4650 4100 4650 4450
+Connection ~ 1400 4850
+Connection ~ 3000 5150
+$Comp
+L SINE v1
+U 1 1 548EB552
+P 1400 4150
+F 0 "v1" H 1200 4250 60 0000 C CNN
+F 1 "SINE" H 1200 4100 60 0000 C CNN
+F 2 "R1" H 1100 4150 60 0000 C CNN
+ 1 1400 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 548EB534
+P 1550 4850
+F 0 "#FLG01" H 1550 5120 30 0001 C CNN
+F 1 "PWR_FLAG" H 1550 5080 30 0000 C CNN
+ 1 1550 4850
+ 1 0 0 -1
+$EndComp
+$Comp
+L VPLOT8_1 U1
+U 2 1 548EB30C
+P 4650 3800
+F 0 "U1" H 4500 3900 50 0000 C CNN
+F 1 "VPLOT8_1" H 4800 3900 50 0000 C CNN
+ 2 4650 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L VPLOT8_1 U1
+U 1 1 548EB307
+P 1400 3150
+F 0 "U1" H 1250 3250 50 0000 C CNN
+F 1 "VPLOT8_1" H 1550 3250 50 0000 C CNN
+ 1 1400 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 548EB261
+P 1400 5250
+F 0 "#PWR02" H 1400 5250 30 0001 C CNN
+F 1 "GND" H 1400 5180 30 0001 C CNN
+ 1 1400 5250
+ 1 0 0 -1
+$EndComp
+$Comp
+L R R1
+U 1 1 548EB228
+P 4650 4700
+F 0 "R1" V 4730 4700 50 0000 C CNN
+F 1 "10k" V 4650 4700 50 0000 C CNN
+ 1 4650 4700
+ 1 0 0 -1
+$EndComp
+$Comp
+L DIODE D4
+U 1 1 548EB19F
+P 3300 4400
+F 0 "D4" H 3300 4500 40 0000 C CNN
+F 1 "1n4007" H 3300 4300 40 0000 C CNN
+ 1 3300 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L DIODE D3
+U 1 1 548EB19B
+P 2400 4400
+F 0 "D3" H 2400 4500 40 0000 C CNN
+F 1 "1n4007" H 2400 4300 40 0000 C CNN
+ 1 2400 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L DIODE D2
+U 1 1 548EB198
+P 3300 3900
+F 0 "D2" H 3300 4000 40 0000 C CNN
+F 1 "1n4007" H 3300 3800 40 0000 C CNN
+ 1 3300 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L DIODE D1
+U 1 1 548EB195
+P 2400 3900
+F 0 "D1" H 2400 4000 40 0000 C CNN
+F 1 "1n4007" H 2400 3800 40 0000 C CNN
+ 1 2400 3900
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/pdf/1/1 FWR/FWR.cir b/pdf/1/1 FWR/FWR.cir
new file mode 100755
index 0000000..a18fcc7
--- /dev/null
+++ b/pdf/1/1 FWR/FWR.cir
@@ -0,0 +1,16 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: 12/15/2014 4:07:39 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+U2 2 3 VPLOT8
+v1 1 0 SINE
+U1 1 VPLOT8_1
+R1 2 3 10k
+D4 0 2 1n4007
+D3 3 0 1n4007
+D2 1 2 1n4007
+D1 3 1 1n4007
+
+.end
diff --git a/pdf/1/1 FWR/FWR.cir.ckt b/pdf/1/1 FWR/FWR.cir.ckt
new file mode 100755
index 0000000..d566c1c
--- /dev/null
+++ b/pdf/1/1 FWR/FWR.cir.ckt
@@ -0,0 +1,14 @@
+* eeschema netlist version 1.1 (spice format) creation date: 12/15/2014 4:07:39 pm
+
+v1 1 0 sine(0 5 50 0 0)
+* Plotting option vplot8_1
+r1 2 3 10k
+d4 0 2 1n4007
+d3 3 0 1n4007
+d2 1 2 1n4007
+d1 3 1 1n4007
+
+.tran 1e-03 100e-03 0e-00
+.plot v(2)-v(3)
+.plot v(1)
+.end
diff --git a/pdf/1/1 FWR/FWR.cir.out b/pdf/1/1 FWR/FWR.cir.out
new file mode 100755
index 0000000..f456fcf
--- /dev/null
+++ b/pdf/1/1 FWR/FWR.cir.out
@@ -0,0 +1,21 @@
+* eeschema netlist version 1.1 (spice format) creation date: 12/15/2014 4:07:39 pm
+
+v1 1 0 sine(0 5 50 0 0)
+* Plotting option vplot8_1
+r1 2 3 10k
+d4 0 2 1n4007
+d3 3 0 1n4007
+d2 1 2 1n4007
+d1 3 1 1n4007
+
+.tran 1e-03 100e-03 0e-00
+
+* Control Statements
+.control
+run
+plot v(2)-v(3)
+plot v(1)
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/pdf/1/1 FWR/FWR.pro b/pdf/1/1 FWR/FWR.pro
new file mode 100755
index 0000000..c2f9628
--- /dev/null
+++ b/pdf/1/1 FWR/FWR.pro
@@ -0,0 +1,74 @@
+update=12/15/2014 3:34:08 PM
+last_client=eeschema
+[eeschema]
+version=1
+LibDir=
+NetFmt=1
+HPGLSpd=20
+HPGLDm=15
+HPGLNum=1
+offX_A4=0
+offY_A4=0
+offX_A3=0
+offY_A3=0
+offX_A2=0
+offY_A2=0
+offX_A1=0
+offY_A1=0
+offX_A0=0
+offY_A0=0
+offX_A=0
+offY_A=0
+offX_B=0
+offY_B=0
+offX_C=0
+offY_C=0
+offX_D=0
+offY_D=0
+offX_E=0
+offY_E=0
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=C:/FreeEDA/FreeEDA/library/analogSpice
+LibName32=C:/FreeEDA/FreeEDA/library/analogXSpice
+LibName33=C:/FreeEDA/FreeEDA/library/convergenceAidSpice
+LibName34=C:/FreeEDA/FreeEDA/library/converterSpice
+LibName35=C:/FreeEDA/FreeEDA/library/digitalSpice
+LibName36=C:/FreeEDA/FreeEDA/library/digitalXSpice
+LibName37=C:/FreeEDA/FreeEDA/library/linearSpice
+LibName38=C:/FreeEDA/FreeEDA/library/measurementSpice
+LibName39=C:/FreeEDA/FreeEDA/library/portSpice
+LibName40=C:/FreeEDA/FreeEDA/library/sourcesSpice
diff --git a/pdf/1/1 FWR/FWR.proj b/pdf/1/1 FWR/FWR.proj
new file mode 100755
index 0000000..68b75c3
--- /dev/null
+++ b/pdf/1/1 FWR/FWR.proj
@@ -0,0 +1 @@
+schematicFile FWR.sch
diff --git a/pdf/1/1 FWR/FWR.sch b/pdf/1/1 FWR/FWR.sch
new file mode 100755
index 0000000..54699d0
--- /dev/null
+++ b/pdf/1/1 FWR/FWR.sch
@@ -0,0 +1,199 @@
+EESchema Schematic File Version 2 date 12/15/2014 4:18:40 PM
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:FWR-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "15 dec 2014"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Connection ~ 5200 5050
+Wire Wire Line
+ 5800 5050 2250 5050
+Wire Wire Line
+ 5800 5050 5800 4000
+Connection ~ 3550 5050
+Connection ~ 1950 4750
+Wire Wire Line
+ 5200 4350 5200 4000
+Wire Wire Line
+ 2250 5050 2250 4050
+Connection ~ 2550 4050
+Wire Wire Line
+ 2250 4050 2550 4050
+Wire Wire Line
+ 1950 4750 3400 4750
+Connection ~ 3400 4300
+Wire Wire Line
+ 3400 4750 3400 4300
+Wire Wire Line
+ 2750 4300 2550 4300
+Wire Wire Line
+ 2550 4300 2550 3800
+Wire Wire Line
+ 2550 3800 2750 3800
+Wire Wire Line
+ 3150 3800 3650 3800
+Wire Wire Line
+ 4050 3800 4200 3800
+Wire Wire Line
+ 4200 3800 4200 4300
+Wire Wire Line
+ 4200 4300 4050 4300
+Wire Wire Line
+ 3150 4300 3650 4300
+Wire Wire Line
+ 3400 3800 3400 3350
+Connection ~ 3400 3800
+Wire Wire Line
+ 5200 4000 4200 4000
+Connection ~ 4200 4000
+Wire Wire Line
+ 3400 3350 1950 3350
+Wire Wire Line
+ 1950 3350 1950 3600
+Wire Wire Line
+ 5200 5050 5200 4850
+Connection ~ 2100 4750
+Connection ~ 4100 5050
+Wire Wire Line
+ 1950 4500 1950 5150
+$Comp
+L VPLOT8 U2
+U 1 1 548EB9B9
+P 5500 4000
+F 0 "U2" H 5350 4100 50 0000 C CNN
+F 1 "VPLOT8" H 5650 4100 50 0000 C CNN
+ 1 5500 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L SINE v1
+U 1 1 548EB552
+P 1950 4050
+F 0 "v1" H 1750 4150 60 0000 C CNN
+F 1 "SINE" H 1750 4000 60 0000 C CNN
+F 2 "R1" H 1650 4050 60 0000 C CNN
+ 1 1950 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 548EB534
+P 2100 4750
+F 0 "#FLG01" H 2100 5020 30 0001 C CNN
+F 1 "PWR_FLAG" H 2100 4980 30 0000 C CNN
+ 1 2100 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L VPLOT8_1 U1
+U 1 1 548EB307
+P 1950 3050
+F 0 "U1" H 1800 3150 50 0000 C CNN
+F 1 "VPLOT8_1" H 2100 3150 50 0000 C CNN
+ 1 1950 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 548EB261
+P 1950 5150
+F 0 "#PWR02" H 1950 5150 30 0001 C CNN
+F 1 "GND" H 1950 5080 30 0001 C CNN
+ 1 1950 5150
+ 1 0 0 -1
+$EndComp
+$Comp
+L R R1
+U 1 1 548EB228
+P 5200 4600
+F 0 "R1" V 5280 4600 50 0000 C CNN
+F 1 "10k" V 5200 4600 50 0000 C CNN
+ 1 5200 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L DIODE D4
+U 1 1 548EB19F
+P 3850 4300
+F 0 "D4" H 3850 4400 40 0000 C CNN
+F 1 "1n4007" H 3850 4200 40 0000 C CNN
+ 1 3850 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L DIODE D3
+U 1 1 548EB19B
+P 2950 4300
+F 0 "D3" H 2950 4400 40 0000 C CNN
+F 1 "1n4007" H 2950 4200 40 0000 C CNN
+ 1 2950 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L DIODE D2
+U 1 1 548EB198
+P 3850 3800
+F 0 "D2" H 3850 3900 40 0000 C CNN
+F 1 "1n4007" H 3850 3700 40 0000 C CNN
+ 1 3850 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L DIODE D1
+U 1 1 548EB195
+P 2950 3800
+F 0 "D1" H 2950 3900 40 0000 C CNN
+F 1 "1n4007" H 2950 3700 40 0000 C CNN
+ 1 2950 3800
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/pdf/1/1 FWR/FWR_last_input.txt b/pdf/1/1 FWR/FWR_last_input.txt
new file mode 100755
index 0000000..3adc58b
--- /dev/null
+++ b/pdf/1/1 FWR/FWR_last_input.txt
@@ -0,0 +1 @@
+v1 1 0 sine(0 5 50 0 0)
diff --git a/pdf/1/1 FWR/analysis b/pdf/1/1 FWR/analysis
new file mode 100755
index 0000000..5bf79dd
--- /dev/null
+++ b/pdf/1/1 FWR/analysis
@@ -0,0 +1 @@
+.tran 1e-03 100e-03 0e-00
diff --git a/pdf/1/1 FWR/eeschema.exe b/pdf/1/1 FWR/eeschema.exe
new file mode 100755
index 0000000..b3b6d28
--- /dev/null
+++ b/pdf/1/1 FWR/eeschema.exe
Binary files differ
diff --git a/pdf/1/1 FWR/libfftw3-3.dll b/pdf/1/1 FWR/libfftw3-3.dll
new file mode 100755
index 0000000..a8f033a
--- /dev/null
+++ b/pdf/1/1 FWR/libfftw3-3.dll
Binary files differ
diff --git a/pdf/1/1 FWR/ngspice.exe b/pdf/1/1 FWR/ngspice.exe
new file mode 100755
index 0000000..e584114
--- /dev/null
+++ b/pdf/1/1 FWR/ngspice.exe
Binary files differ
diff --git a/pdf/1/1 FWR/plot_data_i.txt b/pdf/1/1 FWR/plot_data_i.txt
new file mode 100755
index 0000000..e9e5f02
--- /dev/null
+++ b/pdf/1/1 FWR/plot_data_i.txt
@@ -0,0 +1,116 @@
+* eeschema netlist version 1.1 (spice format) creation date: 12/15/2014 4:07:39 pm
+Transient Analysis Mon Dec 15 16:08:18 2014
+--------------------------------------------------------------------------------
+Index time alli
+--------------------------------------------------------------------------------
+0 0.000000e+000 3.606493e-039
+1 1.000000e-005 -2.17812e-014
+2 2.000000e-005 -4.43227e-014
+3 4.000000e-005 -9.35520e-014
+4 8.000000e-005 -2.38250e-013
+5 1.600000e-004 -1.53691e-012
+6 3.200000e-004 -1.63800e-010
+7 6.400000e-004 -1.73017e-006
+8 1.280000e-003 -7.78645e-005
+9 2.280000e-003 -2.05364e-004
+10 3.280000e-003 -3.03847e-004
+11 4.280000e-003 -3.61390e-004
+12 5.280000e-003 -3.72083e-004
+13 6.280000e-003 -3.34708e-004
+14 7.280000e-003 -2.53135e-004
+15 8.280000e-003 -1.36494e-004
+16 9.280000e-003 -6.87530e-006
+17 1.028000e-002 4.917472e-011
+18 1.128000e-002 7.780236e-005
+19 1.228000e-002 2.054564e-004
+20 1.328000e-002 3.038616e-004
+21 1.428000e-002 3.615052e-004
+22 1.528000e-002 3.721142e-004
+23 1.628000e-002 3.347006e-004
+24 1.728000e-002 2.531279e-004
+25 1.828000e-002 1.364935e-004
+26 1.928000e-002 6.875297e-006
+27 2.028000e-002 -4.91747e-011
+28 2.128000e-002 -7.78024e-005
+29 2.228000e-002 -2.05456e-004
+30 2.328000e-002 -3.03862e-004
+31 2.428000e-002 -3.61505e-004
+32 2.528000e-002 -3.72114e-004
+33 2.628000e-002 -3.34701e-004
+34 2.728000e-002 -2.53128e-004
+35 2.828000e-002 -1.36493e-004
+36 2.928000e-002 -6.87530e-006
+37 3.028000e-002 4.917472e-011
+38 3.128000e-002 7.780236e-005
+39 3.228000e-002 2.054564e-004
+40 3.328000e-002 3.038616e-004
+41 3.428000e-002 3.615052e-004
+42 3.528000e-002 3.721142e-004
+43 3.628000e-002 3.347006e-004
+44 3.728000e-002 2.531279e-004
+45 3.828000e-002 1.364935e-004
+46 3.928000e-002 6.875297e-006
+47 4.028000e-002 -4.91747e-011
+48 4.128000e-002 -7.78024e-005
+49 4.228000e-002 -2.05456e-004
+50 4.328000e-002 -3.03862e-004
+51 4.428000e-002 -3.61505e-004
+52 4.528000e-002 -3.72114e-004
+53 4.628000e-002 -3.34701e-004
+54 4.728000e-002 -2.53128e-004
+
+Index time alli
+--------------------------------------------------------------------------------
+55 4.828000e-002 -1.36493e-004
+56 4.928000e-002 -6.87530e-006
+57 5.028000e-002 4.917472e-011
+58 5.128000e-002 7.780236e-005
+59 5.228000e-002 2.054564e-004
+60 5.328000e-002 3.038616e-004
+61 5.428000e-002 3.615052e-004
+62 5.528000e-002 3.721142e-004
+63 5.628000e-002 3.347006e-004
+64 5.728000e-002 2.531279e-004
+65 5.828000e-002 1.364935e-004
+66 5.928000e-002 6.875297e-006
+67 6.028000e-002 -4.91747e-011
+68 6.128000e-002 -7.78024e-005
+69 6.228000e-002 -2.05456e-004
+70 6.328000e-002 -3.03862e-004
+71 6.428000e-002 -3.61505e-004
+72 6.528000e-002 -3.72114e-004
+73 6.628000e-002 -3.34701e-004
+74 6.728000e-002 -2.53128e-004
+75 6.828000e-002 -1.36493e-004
+76 6.928000e-002 -6.87530e-006
+77 7.028000e-002 4.917472e-011
+78 7.128000e-002 7.780236e-005
+79 7.228000e-002 2.054564e-004
+80 7.328000e-002 3.038616e-004
+81 7.428000e-002 3.615052e-004
+82 7.528000e-002 3.721142e-004
+83 7.628000e-002 3.347006e-004
+84 7.728000e-002 2.531279e-004
+85 7.828000e-002 1.364935e-004
+86 7.928000e-002 6.875297e-006
+87 8.028000e-002 -4.91747e-011
+88 8.128000e-002 -7.78024e-005
+89 8.228000e-002 -2.05456e-004
+90 8.328000e-002 -3.03862e-004
+91 8.428000e-002 -3.61505e-004
+92 8.528000e-002 -3.72114e-004
+93 8.628000e-002 -3.34701e-004
+94 8.728000e-002 -2.53128e-004
+95 8.828000e-002 -1.36493e-004
+96 8.928000e-002 -6.87530e-006
+97 9.028000e-002 4.917472e-011
+98 9.128000e-002 7.780236e-005
+99 9.228000e-002 2.054564e-004
+100 9.328000e-002 3.038616e-004
+101 9.428000e-002 3.615052e-004
+102 9.528000e-002 3.721142e-004
+103 9.628000e-002 3.347006e-004
+104 9.728000e-002 2.531279e-004
+105 9.828000e-002 1.364935e-004
+106 9.928000e-002 6.875297e-006
+107 1.000000e-001 -2.92819e-026
diff --git a/pdf/1/1 FWR/plot_data_v.txt b/pdf/1/1 FWR/plot_data_v.txt
new file mode 100755
index 0000000..a1dee49
--- /dev/null
+++ b/pdf/1/1 FWR/plot_data_v.txt
@@ -0,0 +1,116 @@
+* eeschema netlist version 1.1 (spice format) creation date: 12/15/2014 4:07:39 pm
+Transient Analysis Mon Dec 15 16:08:18 2014
+--------------------------------------------------------------------------------
+Index time V(1) V(2) V(3)
+--------------------------------------------------------------------------------
+0 0.000000e+000 0.000000e+000 5.056840e-019 5.056855e-019
+1 1.000000e-005 1.570794e-002 7.853969e-003 7.853969e-003
+2 2.000000e-005 3.141572e-002 1.570786e-002 1.570786e-002
+3 4.000000e-005 6.283020e-002 3.141510e-002 3.141510e-002
+4 8.000000e-005 1.256505e-001 6.282524e-002 6.282524e-002
+5 1.600000e-004 2.512216e-001 1.256108e-001 1.256108e-001
+6 3.200000e-004 5.018086e-001 2.509051e-001 2.509035e-001
+7 6.400000e-004 9.985499e-001 5.079258e-001 4.906241e-001
+8 1.280000e-003 1.956868e+000 1.367757e+000 5.891118e-001
+9 2.280000e-003 3.282929e+000 2.668283e+000 6.146463e-001
+10 3.280000e-003 4.287633e+000 3.663052e+000 6.245809e-001
+11 4.280000e-003 4.872634e+000 4.243267e+000 6.293674e-001
+12 5.280000e-003 4.980668e+000 4.350749e+000 6.299189e-001
+13 6.280000e-003 4.601159e+000 3.974118e+000 6.270408e-001
+14 7.280000e-003 3.771257e+000 3.151305e+000 6.199516e-001
+15 8.280000e-003 2.572198e+000 1.968567e+000 6.036309e-001
+16 9.280000e-003 1.121354e+000 5.950534e-001 5.263004e-001
+17 1.028000e-002 -4.39256e-001 -2.19628e-001 -2.19628e-001
+18 1.128000e-002 -1.95687e+000 -5.89422e-001 -1.36745e+000
+19 1.228000e-002 -3.28293e+000 -6.14182e-001 -2.66875e+000
+20 1.328000e-002 -4.28763e+000 -6.24509e-001 -3.66312e+000
+21 1.428000e-002 -4.87263e+000 -6.28791e-001 -4.24384e+000
+22 1.528000e-002 -4.98067e+000 -6.29763e-001 -4.35090e+000
+23 1.628000e-002 -4.60116e+000 -6.27077e-001 -3.97408e+000
+24 1.728000e-002 -3.77126e+000 -6.19989e-001 -3.15127e+000
+25 1.828000e-002 -2.57220e+000 -6.03632e-001 -1.96857e+000
+26 1.928000e-002 -1.12135e+000 -5.26300e-001 -5.95053e-001
+27 2.028000e-002 4.392560e-001 2.196282e-001 2.196277e-001
+28 2.128000e-002 1.956868e+000 1.367446e+000 5.894224e-001
+29 2.228000e-002 3.282929e+000 2.668747e+000 6.141822e-001
+30 2.328000e-002 4.287633e+000 3.663125e+000 6.245087e-001
+31 2.428000e-002 4.872634e+000 4.243843e+000 6.287912e-001
+32 2.528000e-002 4.980668e+000 4.350905e+000 6.297631e-001
+33 2.628000e-002 4.601159e+000 3.974083e+000 6.270766e-001
+34 2.728000e-002 3.771257e+000 3.151268e+000 6.199889e-001
+35 2.828000e-002 2.572198e+000 1.968566e+000 6.036315e-001
+36 2.928000e-002 1.121354e+000 5.950534e-001 5.263004e-001
+37 3.028000e-002 -4.39256e-001 -2.19628e-001 -2.19628e-001
+38 3.128000e-002 -1.95687e+000 -5.89422e-001 -1.36745e+000
+39 3.228000e-002 -3.28293e+000 -6.14182e-001 -2.66875e+000
+40 3.328000e-002 -4.28763e+000 -6.24509e-001 -3.66312e+000
+41 3.428000e-002 -4.87263e+000 -6.28791e-001 -4.24384e+000
+42 3.528000e-002 -4.98067e+000 -6.29763e-001 -4.35090e+000
+43 3.628000e-002 -4.60116e+000 -6.27077e-001 -3.97408e+000
+44 3.728000e-002 -3.77126e+000 -6.19989e-001 -3.15127e+000
+45 3.828000e-002 -2.57220e+000 -6.03632e-001 -1.96857e+000
+46 3.928000e-002 -1.12135e+000 -5.26300e-001 -5.95053e-001
+47 4.028000e-002 4.392560e-001 2.196282e-001 2.196277e-001
+48 4.128000e-002 1.956868e+000 1.367446e+000 5.894224e-001
+49 4.228000e-002 3.282929e+000 2.668747e+000 6.141822e-001
+50 4.328000e-002 4.287633e+000 3.663125e+000 6.245087e-001
+51 4.428000e-002 4.872634e+000 4.243843e+000 6.287912e-001
+52 4.528000e-002 4.980668e+000 4.350905e+000 6.297631e-001
+53 4.628000e-002 4.601159e+000 3.974083e+000 6.270766e-001
+54 4.728000e-002 3.771257e+000 3.151268e+000 6.199889e-001
+
+Index time V(1) V(2) V(3)
+--------------------------------------------------------------------------------
+55 4.828000e-002 2.572198e+000 1.968566e+000 6.036315e-001
+56 4.928000e-002 1.121354e+000 5.950534e-001 5.263004e-001
+57 5.028000e-002 -4.39256e-001 -2.19628e-001 -2.19628e-001
+58 5.128000e-002 -1.95687e+000 -5.89422e-001 -1.36745e+000
+59 5.228000e-002 -3.28293e+000 -6.14182e-001 -2.66875e+000
+60 5.328000e-002 -4.28763e+000 -6.24509e-001 -3.66312e+000
+61 5.428000e-002 -4.87263e+000 -6.28791e-001 -4.24384e+000
+62 5.528000e-002 -4.98067e+000 -6.29763e-001 -4.35090e+000
+63 5.628000e-002 -4.60116e+000 -6.27077e-001 -3.97408e+000
+64 5.728000e-002 -3.77126e+000 -6.19989e-001 -3.15127e+000
+65 5.828000e-002 -2.57220e+000 -6.03632e-001 -1.96857e+000
+66 5.928000e-002 -1.12135e+000 -5.26300e-001 -5.95053e-001
+67 6.028000e-002 4.392560e-001 2.196282e-001 2.196277e-001
+68 6.128000e-002 1.956868e+000 1.367446e+000 5.894224e-001
+69 6.228000e-002 3.282929e+000 2.668747e+000 6.141822e-001
+70 6.328000e-002 4.287633e+000 3.663125e+000 6.245087e-001
+71 6.428000e-002 4.872634e+000 4.243843e+000 6.287912e-001
+72 6.528000e-002 4.980668e+000 4.350905e+000 6.297631e-001
+73 6.628000e-002 4.601159e+000 3.974083e+000 6.270766e-001
+74 6.728000e-002 3.771257e+000 3.151268e+000 6.199889e-001
+75 6.828000e-002 2.572198e+000 1.968566e+000 6.036315e-001
+76 6.928000e-002 1.121354e+000 5.950534e-001 5.263004e-001
+77 7.028000e-002 -4.39256e-001 -2.19628e-001 -2.19628e-001
+78 7.128000e-002 -1.95687e+000 -5.89422e-001 -1.36745e+000
+79 7.228000e-002 -3.28293e+000 -6.14182e-001 -2.66875e+000
+80 7.328000e-002 -4.28763e+000 -6.24509e-001 -3.66312e+000
+81 7.428000e-002 -4.87263e+000 -6.28791e-001 -4.24384e+000
+82 7.528000e-002 -4.98067e+000 -6.29763e-001 -4.35090e+000
+83 7.628000e-002 -4.60116e+000 -6.27077e-001 -3.97408e+000
+84 7.728000e-002 -3.77126e+000 -6.19989e-001 -3.15127e+000
+85 7.828000e-002 -2.57220e+000 -6.03632e-001 -1.96857e+000
+86 7.928000e-002 -1.12135e+000 -5.26300e-001 -5.95053e-001
+87 8.028000e-002 4.392560e-001 2.196282e-001 2.196277e-001
+88 8.128000e-002 1.956868e+000 1.367446e+000 5.894224e-001
+89 8.228000e-002 3.282929e+000 2.668747e+000 6.141822e-001
+90 8.328000e-002 4.287633e+000 3.663125e+000 6.245087e-001
+91 8.428000e-002 4.872634e+000 4.243843e+000 6.287912e-001
+92 8.528000e-002 4.980668e+000 4.350905e+000 6.297631e-001
+93 8.628000e-002 4.601159e+000 3.974083e+000 6.270766e-001
+94 8.728000e-002 3.771257e+000 3.151268e+000 6.199889e-001
+95 8.828000e-002 2.572198e+000 1.968566e+000 6.036315e-001
+96 8.928000e-002 1.121354e+000 5.950534e-001 5.263004e-001
+97 9.028000e-002 -4.39256e-001 -2.19628e-001 -2.19628e-001
+98 9.128000e-002 -1.95687e+000 -5.89422e-001 -1.36745e+000
+99 9.228000e-002 -3.28293e+000 -6.14182e-001 -2.66875e+000
+100 9.328000e-002 -4.28763e+000 -6.24509e-001 -3.66312e+000
+101 9.428000e-002 -4.87263e+000 -6.28791e-001 -4.24384e+000
+102 9.528000e-002 -4.98067e+000 -6.29763e-001 -4.35090e+000
+103 9.628000e-002 -4.60116e+000 -6.27077e-001 -3.97408e+000
+104 9.728000e-002 -3.77126e+000 -6.19989e-001 -3.15127e+000
+105 9.828000e-002 -2.57220e+000 -6.03632e-001 -1.96857e+000
+106 9.928000e-002 -1.12135e+000 -5.26300e-001 -5.95053e-001
+107 1.000000e-001 -6.12323e-015 -1.59483e-009 1.594809e-009
diff --git a/pdf/1/1 FWR/python.exe b/pdf/1/1 FWR/python.exe
new file mode 100755
index 0000000..c72f16d
--- /dev/null
+++ b/pdf/1/1 FWR/python.exe
Binary files differ
diff --git a/pdf/1/1 FWR/vcomp100.dll b/pdf/1/1 FWR/vcomp100.dll
new file mode 100755
index 0000000..e23321c
--- /dev/null
+++ b/pdf/1/1 FWR/vcomp100.dll
Binary files differ
generated by cgit (git 2.34.1) at 2025-03-13 08:32:03 +0000