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author | yash1112 | 2017-07-07 21:20:49 +0530 |
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committer | yash1112 | 2017-07-07 21:20:49 +0530 |
commit | 3f52712f806fbd80d66dfdcaff401e5cf94dcca4 (patch) | |
tree | a8333b8187cb44b505b9fe37fc9a7ac8a1711c10 /src/c/operations/interfaces/int_OpEqual.h | |
download | scilab2c-3f52712f806fbd80d66dfdcaff401e5cf94dcca4.tar.gz scilab2c-3f52712f806fbd80d66dfdcaff401e5cf94dcca4.tar.bz2 scilab2c-3f52712f806fbd80d66dfdcaff401e5cf94dcca4.zip |
sci2c arduino updated
Diffstat (limited to 'src/c/operations/interfaces/int_OpEqual.h')
-rw-r--r-- | src/c/operations/interfaces/int_OpEqual.h | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/src/c/operations/interfaces/int_OpEqual.h b/src/c/operations/interfaces/int_OpEqual.h new file mode 100644 index 00000000..869b28dc --- /dev/null +++ b/src/c/operations/interfaces/int_OpEqual.h @@ -0,0 +1,39 @@ +/* + * Scilab ( http://www.scilab.org/ ) - This file is part of Scilab + * Copyright (C) 2008-2008 - INRIA - Bruno JOFRET + * + * This file must be used under the terms of the CeCILL. + * This source file is licensed as described in the file COPYING, which + * you should have received as part of this distribution. The terms + * are also available at + * http://www.cecill.info/licences/Licence_CeCILL_V2-en.txt + * + */ + +/* THIS IS AN AUTOMATICALLY GENERATED FILE : DO NOT EDIT BY HAND. */ + +#ifndef __INT_OPEQUAL_H__ +#define __INT_OPEQUAL_H__ + + +#define s0OpEquals0(in) in + +#define d0OpEquald0(in) in + +#define c0OpEqualc0(in) in + +#define z0OpEqualz0(in) in + +#define s2OpEquals2(in1,size,out) {int i=0; \ + for (i = 0 ; i<size[0] * size[1] ; i++) out[i]=in1[i]; \ + } + +#define d2OpEquald2(in1,size,out) {int i=0; \ + for (i = 0 ; i<size[0] * size[1] ; i++) out[i]=in1[i]; \ + } + +#define g2OpEqualg2(in1,size,out) {int i=0; \ + for (i = 0 ; i<size[0] * size[1] ; i++) out[i]=in1[i]; \ + } + +#endif /* !__INT_OPEQUAL_H__ */ |