summaryrefslogtreecommitdiff
path: root/src/c/hardware/avr/uart/u16AVRUARTTransmits.c
diff options
context:
space:
mode:
authorAbhinav Dronamraju2017-09-29 22:00:40 +0530
committerAbhinav Dronamraju2017-09-29 22:00:40 +0530
commit9bc7ad78e8d7d7acc4b9387aa592542832e80b31 (patch)
tree7fce060665a91de5e5adb12d02003351c3d1fdfc /src/c/hardware/avr/uart/u16AVRUARTTransmits.c
parent33755eb085a3ca8154cf83773b23fbb8aac4ba3e (diff)
parentac0045f12ad3d0938758e9742f4107a334e1afaa (diff)
downloadscilab2c-9bc7ad78e8d7d7acc4b9387aa592542832e80b31.tar.gz
scilab2c-9bc7ad78e8d7d7acc4b9387aa592542832e80b31.tar.bz2
scilab2c-9bc7ad78e8d7d7acc4b9387aa592542832e80b31.zip
NEW FEATURES AND NEW FUNCTIONS
Diffstat (limited to 'src/c/hardware/avr/uart/u16AVRUARTTransmits.c')
-rw-r--r--src/c/hardware/avr/uart/u16AVRUARTTransmits.c87
1 files changed, 87 insertions, 0 deletions
diff --git a/src/c/hardware/avr/uart/u16AVRUARTTransmits.c b/src/c/hardware/avr/uart/u16AVRUARTTransmits.c
new file mode 100644
index 00000000..3cfb4a27
--- /dev/null
+++ b/src/c/hardware/avr/uart/u16AVRUARTTransmits.c
@@ -0,0 +1,87 @@
+/* Copyright (C) 2016 - IIT Bombay - FOSSEE
+
+ This file must be used under the terms of the CeCILL.
+ This source file is licensed as described in the file COPYING, which
+ you should have received as part of this distribution. The terms
+ are also available at
+ http://www.cecill.info/licences/Licence_CeCILL_V2-en.txt
+ Author: Ashish Kamble
+ Organization: FOSSEE, IIT Bombay
+ Email: toolbox@scilab.in
+*/
+//Function to Transmit Unsigned Integer Values.
+
+#include "AVRPeripheralUART.h"
+
+uint8 u16AVRUARTTransmits(uint16 data)
+{
+ uint8 temp1;
+ uint8 temp2;
+ uint8 temp3;
+ uint8 temp4;
+ uint8 temp5;
+ temp1 = data/10000;
+ if(temp1==0);
+ else
+ {
+ while ( !( UCSRA & (1<<UDRE)) ) ; // Wait for empty transmit buffer
+ UDR = (48+temp1); // Put data into buffer, sends the data
+ }
+ data = data % 10000;
+ temp2 = data/1000;
+ if((temp1==0)&(temp2==0));
+ else
+ {
+ while ( !( UCSRA & (1<<UDRE)) ) ; // Wait for empty transmit buffer
+ UDR = (48+temp2); // Put data into buffer, sends the data
+ }
+ data = data % 1000;
+ temp3 = data/100;
+ if((temp1==0)&(temp2==0)&(temp3==0));
+ else
+ {
+ while ( !( UCSRA & (1<<UDRE)) ) ; // Wait for empty transmit buffer
+ UDR = (48+temp3); // Put data into buffer, sends the data
+ }
+ data = data % 100;
+ temp4 = data/10;
+ if((temp1==0)&(temp2==0)&(temp3==0)&(temp4==0));
+ else
+ {
+ while ( !( UCSRA & (1<<UDRE)) ) ; // Wait for empty transmit buffer
+ UDR = (48+temp4); // Put data into buffer, sends the data
+ }
+ temp5 = data % 10;
+ while ( !( UCSRA & (1<<UDRE)) ) ; // Wait for empty transmit buffer
+ UDR = (48+temp5); // Put data into buffer, sends the data
+
+
+ while ( !( UCSRA & (1<<UDRE)) ) ; // Wait for empty transmit buffer
+ UDR = (10); // Put data into buffer, sends the data
+ while ( !( UCSRA & (1<<UDRE)) ) ; // Wait for empty transmit buffer
+ UDR = (13); // Put data into buffer, sends the data
+ return 0;
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+