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author | Abhinav Dronamraju | 2017-09-29 22:00:40 +0530 |
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committer | Abhinav Dronamraju | 2017-09-29 22:00:40 +0530 |
commit | 9bc7ad78e8d7d7acc4b9387aa592542832e80b31 (patch) | |
tree | 7fce060665a91de5e5adb12d02003351c3d1fdfc /src/c/hardware/avr/pwm | |
parent | 33755eb085a3ca8154cf83773b23fbb8aac4ba3e (diff) | |
parent | ac0045f12ad3d0938758e9742f4107a334e1afaa (diff) | |
download | scilab2c-9bc7ad78e8d7d7acc4b9387aa592542832e80b31.tar.gz scilab2c-9bc7ad78e8d7d7acc4b9387aa592542832e80b31.tar.bz2 scilab2c-9bc7ad78e8d7d7acc4b9387aa592542832e80b31.zip |
NEW FEATURES AND NEW FUNCTIONS
Diffstat (limited to 'src/c/hardware/avr/pwm')
-rw-r--r-- | src/c/hardware/avr/pwm/u8AVRPWM0SetDutys.c | 24 | ||||
-rw-r--r-- | src/c/hardware/avr/pwm/u8AVRPWM0Setups.c | 50 | ||||
-rw-r--r-- | src/c/hardware/avr/pwm/u8AVRPWM1SetDutys.c | 31 | ||||
-rw-r--r-- | src/c/hardware/avr/pwm/u8AVRPWM1Setups.c | 69 | ||||
-rw-r--r-- | src/c/hardware/avr/pwm/u8AVRPWM2SetDutys.c | 22 | ||||
-rw-r--r-- | src/c/hardware/avr/pwm/u8AVRPWM2Setups.c | 47 |
6 files changed, 243 insertions, 0 deletions
diff --git a/src/c/hardware/avr/pwm/u8AVRPWM0SetDutys.c b/src/c/hardware/avr/pwm/u8AVRPWM0SetDutys.c new file mode 100644 index 00000000..106a872e --- /dev/null +++ b/src/c/hardware/avr/pwm/u8AVRPWM0SetDutys.c @@ -0,0 +1,24 @@ +/* Copyright (C) 2016 - IIT Bombay - FOSSEE + + This file must be used under the terms of the CeCILL. + This source file is licensed as described in the file COPYING, which + you should have received as part of this distribution. The terms + are also available at + http://www.cecill.info/licences/Licence_CeCILL_V2-en.txt + Author: Ashish Kamble + Organization: FOSSEE, IIT Bombay + Email: toolbox@scilab.in +*/ +//Function to Set Duty cycle of PWM Output generated by Timer0 at OC0 pin. + + +#include "AVRPeripheralPWM.h" + +uint8 u8AVRPWM0SetDutys(uint8 duty) +{ + uint8 duty_value = 0; + duty_value = (((uint16)(duty * 0xff))/100); + OCR0 = duty_value; + return 0; +} + diff --git a/src/c/hardware/avr/pwm/u8AVRPWM0Setups.c b/src/c/hardware/avr/pwm/u8AVRPWM0Setups.c new file mode 100644 index 00000000..131ee68b --- /dev/null +++ b/src/c/hardware/avr/pwm/u8AVRPWM0Setups.c @@ -0,0 +1,50 @@ +/* Copyright (C) 2016 - IIT Bombay - FOSSEE + + This file must be used under the terms of the CeCILL. + This source file is licensed as described in the file COPYING, which + you should have received as part of this distribution. The terms + are also available at + http://www.cecill.info/licences/Licence_CeCILL_V2-en.txt + Author: Ashish Kamble + Organization: FOSSEE, IIT Bombay + Email: toolbox@scilab.in +*/ +//Function to Setup PWM output for OC0 pin. + + +#include "AVRPeripheralPWM.h" + + +uint8 u8AVRPWM0Setups(uint8 waveform_mode, uint8 output_mode) +{ + switch(waveform_mode) + { + case 0: + TCCR0 |= (1<<WGM00); + break; + + case 1: + TCCR0 |= (1<<WGM00)|(1<<WGM01); + break; + + case 2: + TCCR0 |= (1<<WGM01); + break; + } + switch(output_mode) + { + case 0: + TCCR0 |= (1<<COM01); + break; + + case 1: + TCCR0 |= (1<<COM00)|(1<<COM01); + break; + + case 2: + TCCR0 |= (1<<COM00); + break; + } + return 0; +} + diff --git a/src/c/hardware/avr/pwm/u8AVRPWM1SetDutys.c b/src/c/hardware/avr/pwm/u8AVRPWM1SetDutys.c new file mode 100644 index 00000000..47aad1c8 --- /dev/null +++ b/src/c/hardware/avr/pwm/u8AVRPWM1SetDutys.c @@ -0,0 +1,31 @@ +/* Copyright (C) 2016 - IIT Bombay - FOSSEE + + This file must be used under the terms of the CeCILL. + This source file is licensed as described in the file COPYING, which + you should have received as part of this distribution. The terms + are also available at + http://www.cecill.info/licences/Licence_CeCILL_V2-en.txt + Author: Ashish Kamble + Organization: FOSSEE, IIT Bombay + Email: toolbox@scilab.in +*/ +//Function to Set Duty cycle and Top Value of PWM Output generated by Timer1 at OC1A or OC1B pin. + +#include "AVRPeripheralPWM.h" + +uint8 u8AVRPWM1SetDutys(uint8 output_pin, uint16 duty, uint16 Top_Value) +{ + uint16 duty_value = 0; + ICR1 = Top_Value; + if(output_pin==0) + { + duty_value = (((uint16)(duty * Top_Value))/100); + OCR1A = duty_value; + } + else if(output_pin==1) + { + duty_value = (((uint16)(duty * Top_Value))/100); + OCR1B = duty_value; + } + return 0; +} diff --git a/src/c/hardware/avr/pwm/u8AVRPWM1Setups.c b/src/c/hardware/avr/pwm/u8AVRPWM1Setups.c new file mode 100644 index 00000000..b3f2d8f4 --- /dev/null +++ b/src/c/hardware/avr/pwm/u8AVRPWM1Setups.c @@ -0,0 +1,69 @@ +/* Copyright (C) 2016 - IIT Bombay - FOSSEE + + This file must be used under the terms of the CeCILL. + This source file is licensed as described in the file COPYING, which + you should have received as part of this distribution. The terms + are also available at + http://www.cecill.info/licences/Licence_CeCILL_V2-en.txt + Author: Ashish Kamble + Organization: FOSSEE, IIT Bombay + Email: toolbox@scilab.in +*/ +//Function to Setup PWM output for OC1A or OC1B pin. + +#include "AVRPeripheralPWM.h" + +uint8 u8AVRPWM1Setups(uint8 waveform_mode, uint8 output_mode, uint8 output_pin) +{ + switch(waveform_mode) + { + case 0: + TCCR1A |= (1<<WGM11); + TCCR1B |= (1<<WGM13); + break; + + case 1: + TCCR1A |= (1<<WGM11); + TCCR1B |= (1<<WGM12)|(1<<WGM13); + break; + + case 2: + TCCR1B |= (1<<WGM12)|(1<<WGM13); + break; + } + if(output_pin==0) + { + switch(output_mode) + { + case 0: + TCCR1A |= (1<<COM1A1); + break; + + case 1: + TCCR1A |= (1<<COM1A0)|(1<<COM1A1); + break; + + case 2: + TCCR1A |= (1<<COM1A0); + break; + } + } + else if(output_pin==1) + { + switch(output_mode==0) + { + case 0: + TCCR1A |= (1<<COM1B1); + break; + + case 1: + TCCR1A |= (1<<COM1B0)|(1<<COM1B1); + break; + + case 2: + TCCR1A |= (1<<COM1B0); + break; + } + } + return 0; +} diff --git a/src/c/hardware/avr/pwm/u8AVRPWM2SetDutys.c b/src/c/hardware/avr/pwm/u8AVRPWM2SetDutys.c new file mode 100644 index 00000000..e0b53186 --- /dev/null +++ b/src/c/hardware/avr/pwm/u8AVRPWM2SetDutys.c @@ -0,0 +1,22 @@ +/* Copyright (C) 2016 - IIT Bombay - FOSSEE + + This file must be used under the terms of the CeCILL. + This source file is licensed as described in the file COPYING, which + you should have received as part of this distribution. The terms + are also available at + http://www.cecill.info/licences/Licence_CeCILL_V2-en.txt + Author: Ashish Kamble + Organization: FOSSEE, IIT Bombay + Email: toolbox@scilab.in +*/ +//Function to Set Duty cycle of PWM Output generated by Timer2 at OC2 pin. + +#include "AVRPeripheralPWM.h" + +uint8 u8AVRPWM2SetDutys(uint8 duty) +{ + uint8 duty_value = 0; + duty_value = (uint8)(((uint16)(duty * 0xff))/100); + OCR2 = duty_value; + return 0; +} diff --git a/src/c/hardware/avr/pwm/u8AVRPWM2Setups.c b/src/c/hardware/avr/pwm/u8AVRPWM2Setups.c new file mode 100644 index 00000000..f5f87672 --- /dev/null +++ b/src/c/hardware/avr/pwm/u8AVRPWM2Setups.c @@ -0,0 +1,47 @@ +/* Copyright (C) 2016 - IIT Bombay - FOSSEE + + This file must be used under the terms of the CeCILL. + This source file is licensed as described in the file COPYING, which + you should have received as part of this distribution. The terms + are also available at + http://www.cecill.info/licences/Licence_CeCILL_V2-en.txt + Author: Ashish Kamble + Organization: FOSSEE, IIT Bombay + Email: toolbox@scilab.in +*/ +//Function to Setup PWM output for OC2 pin. + +#include "AVRPeripheralPWM.h" + +uint8 u8AVRPWM2Setups(uint8 waveform_mode, uint8 output_mode) +{ + switch(waveform_mode) + { + case 0: + TCCR2 |= (1<<WGM20); + break; + + case 1: + TCCR2 |= (1<<WGM20)|(1<<WGM21); + break; + + case 2: + TCCR2 |= (1<<WGM21); + break; + } + switch(output_mode) + { + case 0: + TCCR2 |= (1<<COM21); + break; + + case 1: + TCCR2 |= (1<<COM20)|(1<<COM21); + break; + + case 2: + TCCR2 |= (1<<COM20); + break; + } + return 0; +} |