Intermediate commit aith support added for AVR (GPIO,ADC). Does not support other targets.

1 files changed, 34 insertions, 0 deletions

diff --git a/builder.sce b/builder.sce
new file mode 100644
index 00000000..71523a6b
--- /dev/null
+++ b/builder.sce
@@ -0,0 +1,34 @@
+//
+// Scilab ( http://www.scilab.org/ ) - This file is part of Scilab
+// Copyright (C) 2009-2009 - DIGITEO - Bruno JOFRET
+//
+// This file must be used under the terms of the CeCILL.
+// This source file is licensed as described in the file COPYING, which
+// you should have received as part of this distribution.  The terms
+// are also available at
+// http://www.cecill.info/licences/Licence_CeCILL_V2-en.txt
+//
+//
+//mode(-1);
+lines(0);
+try
+ getversion('scilab');
+catch
+ error(gettext('Scilab 5.0 or more is required.'));
+end;
+// ====================================================================
+if ~with_module('development_tools') then
+  error(msprintf(gettext('%s module not installed."),'development_tools'));
+end
+// ====================================================================
+TOOLBOX_NAME = 'scilab2c';
+TOOLBOX_TITLE = 'Scilab 2 C Converter';
+// ====================================================================
+toolbox_dir = get_absolute_file_path('builder.sce');
+
+tbx_builder_macros(toolbox_dir);
+//tbx_builder_help(toolbox_dir);
+tbx_build_loader(TOOLBOX_NAME, toolbox_dir);
+
+clear toolbox_dir TOOLBOX_NAME TOOLBOX_TITLE;
+// ====================================================================