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author | Vishnu Easwaran E | 2020-05-27 21:50:09 +0530 |
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committer | Vishnu Easwaran E | 2020-05-27 21:50:09 +0530 |
commit | e073a85cfade909d7f8308fe25b99cc38767ccf5 (patch) | |
tree | 838d17c3b8f707791ac227df25e57ae88c306e3d /MyLibrary | |
parent | 3a5c316e700907a613dc5dde8165157f89853a29 (diff) | |
download | openplc_v2-e073a85cfade909d7f8308fe25b99cc38767ccf5.tar.gz openplc_v2-e073a85cfade909d7f8308fe25b99cc38767ccf5.tar.bz2 openplc_v2-e073a85cfade909d7f8308fe25b99cc38767ccf5.zip |
[vishnu] reordered i/p resistors. Added berg strips to local library.
Diffstat (limited to 'MyLibrary')
-rw-r--r-- | MyLibrary/fossee_openplc.dcm | 6 | ||||
-rw-r--r-- | MyLibrary/fossee_openplc.lib | 26 | ||||
-rw-r--r-- | MyLibrary/fossee_openplc.pretty/bergStrip_1x04_P2.54mm_Vertical.kicad_mod | 37 |
3 files changed, 69 insertions, 0 deletions
diff --git a/MyLibrary/fossee_openplc.dcm b/MyLibrary/fossee_openplc.dcm index b6a562a..f6ec15d 100644 --- a/MyLibrary/fossee_openplc.dcm +++ b/MyLibrary/fossee_openplc.dcm @@ -175,6 +175,12 @@ K Darlington transistor array F http://www.ti.com/lit/ds/symlink/uln2803a.pdf $ENDCMP # +$CMP bergStrip_01x04_Male +D Generic connector, single row, 01x04, script generated (kicad-library-utils/schlib/autogen/connector/) +K connector +F ~ +$ENDCMP +# $CMP opt_isolator_PC847 D Quad DC Optocoupler, Vce 35V, CTR 50%, DIP-16 K NPN DC Quad Optocoupler diff --git a/MyLibrary/fossee_openplc.lib b/MyLibrary/fossee_openplc.lib index ccd6bff..d01eaad 100644 --- a/MyLibrary/fossee_openplc.lib +++ b/MyLibrary/fossee_openplc.lib @@ -819,6 +819,32 @@ X GND 9 0 -700 100 U 50 50 1 1 W ENDDRAW ENDDEF # +# bergStrip_01x04_Male +# +DEF bergStrip_01x04_Male J 0 40 Y N 1 F N +F0 "J" 0 200 50 H V C CNN +F1 "bergStrip_01x04_Male" 0 -300 50 H V C CNN +F2 "fossee_openplc:bergStrip_1x04_P2.54mm_Vertical" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Connector*:*_1x??_* +$ENDFPLIST +DRAW +S 34 -195 0 -205 1 1 6 F +S 34 -95 0 -105 1 1 6 F +S 34 5 0 -5 1 1 6 F +S 34 105 0 95 1 1 6 F +P 2 1 1 6 50 -200 34 -200 N +P 2 1 1 6 50 -100 34 -100 N +P 2 1 1 6 50 0 34 0 N +P 2 1 1 6 50 100 34 100 N +X Pin_1 1 200 100 150 L 50 50 1 1 P +X Pin_2 2 200 0 150 L 50 50 1 1 P +X Pin_3 3 200 -100 150 L 50 50 1 1 P +X Pin_4 4 200 -200 150 L 50 50 1 1 P +ENDDRAW +ENDDEF +# # opt_isolator_PC847 # DEF opt_isolator_PC847 U 0 40 Y Y 4 F N diff --git a/MyLibrary/fossee_openplc.pretty/bergStrip_1x04_P2.54mm_Vertical.kicad_mod b/MyLibrary/fossee_openplc.pretty/bergStrip_1x04_P2.54mm_Vertical.kicad_mod new file mode 100644 index 0000000..63b7cf8 --- /dev/null +++ b/MyLibrary/fossee_openplc.pretty/bergStrip_1x04_P2.54mm_Vertical.kicad_mod @@ -0,0 +1,37 @@ +(module bergStrip_1x04_P2.54mm_Vertical (layer F.Cu) (tedit 5ECE7B6C) + (descr "Through hole straight pin header, 1x04, 2.54mm pitch, single row") + (tags "Through hole pin header THT 1x04 2.54mm single row") + (fp_text reference REF** (at 0 -2.33) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value bergStrip_1x04_P2.54mm_Vertical (at 0 9.95) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 3.81 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.8 9.4) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.8 9.4) (end 1.8 9.4) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.8 -1.8) (end -1.8 9.4) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.33 1.27) (end 1.33 8.95) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 1.27) (end -1.33 8.95) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 8.95) (end 1.33 8.95) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 8.89) (end -1.27 -0.635) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 8.89) (end -1.27 8.89) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 -1.27) (end 1.27 8.89) (layer F.Fab) (width 0.1)) + (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1)) + (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x04_P2.54mm_Vertical.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) |