Example/logic_gates/nor_gate.vhdl


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library ieee;
use ieee.std_logic_1164.all;

entity nor_gate is
    port (a : in  std_logic;
          b : in  std_logic;
          c : out std_logic);
end nor_gate;
     
architecture rtl of nor_gate is
    begin
		c <= a nor b;
end rtl;