Example/2-bit-inverter/inverter.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14

library ieee;
use ieee.std_logic_1164.all;

entity inverter is
    port ( i: in std_logic_vector(1 downto 0);
           o: out std_logic_vector(1 downto 0));
end inverter;

architecture inverter_beh of inverter is
begin
    o <= not i;
end architecture;