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Diffstat (limited to 'Example/full_adder/full_adder_sl.vhdl')
-rw-r--r-- | Example/full_adder/full_adder_sl.vhdl | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/Example/full_adder/full_adder_sl.vhdl b/Example/full_adder/full_adder_sl.vhdl deleted file mode 100644 index a0495f0..0000000 --- a/Example/full_adder/full_adder_sl.vhdl +++ /dev/null @@ -1,19 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity full_adder_slv is - port ( - i_bit1 : in std_logic_vector(0 downto 0); - i_bit2 : in std_logic_vector(0 downto 0); - i_bit3 : in std_logic_vector(0 downto 0); - o_sum : out std_logic_vector(0 downto 0); - o_carry : out std_logic_vector(0 downto 0) - ); -end full_adder_slv; - -architecture rtl of full_adder_slv is -begin - o_sum <= i_bit1 xor i_bit2 xor i_bit3; - o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1); -end rtl; |