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-rw-r--r--Example/bin_to_gray/bin_to_gray.vhdl4
1 files changed, 2 insertions, 2 deletions
diff --git a/Example/bin_to_gray/bin_to_gray.vhdl b/Example/bin_to_gray/bin_to_gray.vhdl
index 542f7ec..d6045e8 100644
--- a/Example/bin_to_gray/bin_to_gray.vhdl
+++ b/Example/bin_to_gray/bin_to_gray.vhdl
@@ -3,8 +3,8 @@ USE ieee.std_logic_1164.ALL;
entity bin_to_gray is
port(
- bin : in std_logic_vector(3 downto 0); -- binary input
- G : out std_logic_vector(3 downto 0) -- gray code output
+ bin : in std_logic_vector(3 downto 0);
+ G : out std_logic_vector(3 downto 0)
);
end bin_to_gray;