diff options
18 files changed, 138 insertions, 51 deletions
diff --git a/Example/README.md b/Example/README.md deleted file mode 100644 index e3eb0cf..0000000 --- a/Example/README.md +++ /dev/null @@ -1,9 +0,0 @@ -Instructions on how to use the examples provided here: -1. Go to eSim main window -> Click on NGHDL icon from the left toolbar, click on the 'browse' button, go to ../nghdl/Example/ and locate which example you wish to simulate. -2. After opening the directory of desired example, locate the vhdl file , click on the "Open" button at the bottom of "Open File" window. -3. Click on 'upload' button in the NGHDL pop-up window. File will be processed in the backend for few seconds. Now exit the NGHDL window. -4. Open the desired example in eSim using the Open Project button, double click on it when the project is loaded in the "Projects" window. -5. Click on the "Simulation" button on eSim Main window. - -NGHDL feature is still under development. More examples will be added by eSim team along the way. -If you have a good command on VHDL and electronics, please feel free to contribute. diff --git a/Example/bin_to_gray/bin_to_gray.vhdl b/Example/combinational_logic/bin_to_gray/bin_to_gray.vhdl index d6045e8..d6045e8 100644 --- a/Example/bin_to_gray/bin_to_gray.vhdl +++ b/Example/combinational_logic/bin_to_gray/bin_to_gray.vhdl diff --git a/Example/counter/up_counter_slv.vhdl b/Example/combinational_logic/counter/counter.vhdl index afef463..ba14df8 100644 --- a/Example/counter/up_counter_slv.vhdl +++ b/Example/combinational_logic/counter/counter.vhdl @@ -1,23 +1,29 @@ library ieee; + use ieee.std_logic_1164.all; use ieee.numeric_std.all; -entity up_counter_slv is +entity counter is port(C : in std_logic; CLR : in std_logic; Q : out std_logic_vector(3 downto 0)); -end up_counter_slv; +end counter; + +architecture bhv of counter is -architecture bhv of up_counter_slv is signal tmp: std_logic_vector(3 downto 0); begin process (C, CLR) + begin if (CLR='1') then - tmp <= "0000"; + tmp <= "0000"; + elsif (C'event and C='1') then - tmp <= std_logic_vector(to_unsigned(1+to_integer(unsigned(tmp)), tmp'length)); + tmp <= std_logic_vector(to_unsigned(1+to_integer(unsigned(tmp)), tmp'length)); + end if; + end process; Q <= tmp; diff --git a/Example/combinational_logic/counter/updown_counter.vhdl b/Example/combinational_logic/counter/updown_counter.vhdl new file mode 100644 index 0000000..922ee67 --- /dev/null +++ b/Example/combinational_logic/counter/updown_counter.vhdl @@ -0,0 +1,32 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + + +entity updown_counter is + Port ( clk: in std_logic; + reset: in std_logic; + up_down: in std_logic; + counter: out std_logic_vector(3 downto 0) + ); +end updown_counter; + +architecture Behavioral of updown_counter is +signal tmp: std_logic_vector(3 downto 0); +begin + +process(clk,reset) +begin + if(reset='1') then + tmp <= "0000"; + elsif(clk'event and clk='1') then + if(up_down='1') then + tmp <= std_logic_vector(to_unsigned(to_integer(unsigned(tmp)-1), tmp'length)); + else + tmp <= std_logic_vector(to_unsigned(to_integer(unsigned(tmp)+1), tmp'length)); + end if; + end if; +end process; + counter <= std_logic_vector(tmp); + +end Behavioral;
\ No newline at end of file diff --git a/Example/decoder/decoder.vhdl b/Example/combinational_logic/decoder/decoder.vhdl index e429ec9..e429ec9 100644 --- a/Example/decoder/decoder.vhdl +++ b/Example/combinational_logic/decoder/decoder.vhdl diff --git a/Example/full_adder/full_adder_sl.vhdl b/Example/combinational_logic/full_adder/full_adder_sl.vhdl index e830563..e830563 100644 --- a/Example/full_adder/full_adder_sl.vhdl +++ b/Example/combinational_logic/full_adder/full_adder_sl.vhdl diff --git a/Example/full_adder/full_adder_sl_slv.vhdl b/Example/combinational_logic/full_adder/full_adder_sl_slv.vhdl index 7de9c1b..7de9c1b 100644 --- a/Example/full_adder/full_adder_sl_slv.vhdl +++ b/Example/combinational_logic/full_adder/full_adder_sl_slv.vhdl diff --git a/Example/full_adder/full_adder_slv.vhdl b/Example/combinational_logic/full_adder/full_adder_slv.vhdl index a0495f0..a0495f0 100644 --- a/Example/full_adder/full_adder_slv.vhdl +++ b/Example/combinational_logic/full_adder/full_adder_slv.vhdl diff --git a/Example/full_adder/full_adder_structural.vhdl b/Example/combinational_logic/full_adder/full_adder_structural.vhdl index eb06a3d..eb06a3d 100644 --- a/Example/full_adder/full_adder_structural.vhdl +++ b/Example/combinational_logic/full_adder/full_adder_structural.vhdl diff --git a/Example/half_adder/half_adder.vhdl b/Example/combinational_logic/half_adder/half_adder.vhdl index 71ef1cc..71ef1cc 100644 --- a/Example/half_adder/half_adder.vhdl +++ b/Example/combinational_logic/half_adder/half_adder.vhdl diff --git a/Example/mux-demux/demux.vhdl b/Example/combinational_logic/mux-demux/demux.vhdl index e73c196..e73c196 100644 --- a/Example/mux-demux/demux.vhdl +++ b/Example/combinational_logic/mux-demux/demux.vhdl diff --git a/Example/mux-demux/mux.vhdl b/Example/combinational_logic/mux-demux/mux.vhdl index b72e287..b72e287 100644 --- a/Example/mux-demux/mux.vhdl +++ b/Example/combinational_logic/mux-demux/mux.vhdl diff --git a/Example/counter/up_counter.vhdl b/Example/counter/up_counter.vhdl deleted file mode 100644 index bd27fcf..0000000 --- a/Example/counter/up_counter.vhdl +++ /dev/null @@ -1,34 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity up_counter is - port(Clock : in std_logic; - CLR : in std_logic; - Q : out std_logic_vector(3 downto 0)); -end up_counter; - -architecture beh of up_counter is - signal tmp: unsigned(3 downto 0) := "0000"; - - --------------- Other ways to initialize -------------- - -- signal tmp: unsigned(3 downto 0) := x"0"; - -- signal tmp: unsigned(3 downto 0) := (others => '0'); - ------------------------------------------------------- - - begin - process (Clock, CLR) - begin - if (CLR='1') then - tmp <= "0000"; - elsif (Clock'event and Clock='1') then - if tmp="1111" then - tmp <= x"0"; - else - tmp <= tmp +1; - end if; - end if; - end process; - - Q <= std_logic_vector (tmp); -end beh;
\ No newline at end of file diff --git a/Example/logic_gates/and_gate.vhdl b/Example/logic_gates/and_gate.vhdl new file mode 100644 index 0000000..689bcba --- /dev/null +++ b/Example/logic_gates/and_gate.vhdl @@ -0,0 +1,33 @@ +library ieee; + +use ieee.std_logic_1164.all; + +entity and_gate is + +port( a: in std_logic; + b: in std_logic; + c: out std_logic +); + +end and_gate; + +architecture beh of and_gate is + + begin + + process(a, b) + + begin + + if (a='1' and b='1') then + c <= '1'; + + else + + c <= '0'; + + end if; + + end process; + +end beh; diff --git a/Example/logic_gates/inverter_gate.vhdl b/Example/logic_gates/inverter.vhdl index 9825917..ee2d830 100644 --- a/Example/logic_gates/inverter_gate.vhdl +++ b/Example/logic_gates/inverter.vhdl @@ -1,12 +1,12 @@ library ieee; use ieee.std_logic_1164.all; -entity inverter_gate is +entity inverter is port ( i: in std_logic; o: out std_logic); -end inverter_gate; +end inverter; -architecture beh of inverter_gate is +architecture beh of inverter is begin o <= not i; end beh; diff --git a/Example/logic_gates/nand_gate.vhdl b/Example/logic_gates/nand_gate.vhdl new file mode 100644 index 0000000..3736285 --- /dev/null +++ b/Example/logic_gates/nand_gate.vhdl @@ -0,0 +1,33 @@ +library ieee; + +use ieee.std_logic_1164.all; + +entity nand_gate is + +port( a: in std_logic; + b: in std_logic; + c: out std_logic +); + +end nand_gate; + +architecture beh of nand_gate is + + begin + + process(a, b) + + begin + + if (a='1' and b='1') then + c <= '0'; + + else + + c <= '1'; + + end if; + + end process; + +end beh; diff --git a/Example/logic_gates/nor_gate.vhdl b/Example/logic_gates/nor_gate.vhdl new file mode 100644 index 0000000..0dcdab0 --- /dev/null +++ b/Example/logic_gates/nor_gate.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity nor_gate is + port (a : in std_logic; + b : in std_logic; + c : out std_logic); +end nor_gate; + +architecture rtl of nor_gate is + begin + c <= a nor b; +end rtl; diff --git a/Example/logic_gates/or_gate.vhdl b/Example/logic_gates/or_gate.vhdl new file mode 100644 index 0000000..d470c3d --- /dev/null +++ b/Example/logic_gates/or_gate.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity or_gate is + Port ( a : in STD_LOGIC; + b : in STD_LOGIC; + c : out STD_LOGIC); +end or_gate; + +architecture behavioral of or_gate is +begin +c <= a or b; +end behavioral; |