summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorambikeshwar2015-08-13 15:41:17 +0530
committerambikeshwar2015-08-13 15:41:17 +0530
commit7db80ad75fc9b1e2444fdf8626d58f3241e60c1b (patch)
treeb165aa80a9ce2a01225e84618e7ca32eb2ba84a5 /src
parent1a2466cd700138ed4703de24fd02b7ff6e78b303 (diff)
downloadnghdl-7db80ad75fc9b1e2444fdf8626d58f3241e60c1b.tar.gz
nghdl-7db80ad75fc9b1e2444fdf8626d58f3241e60c1b.tar.bz2
nghdl-7db80ad75fc9b1e2444fdf8626d58f3241e60c1b.zip
content of testbench has been changed in accordance to accomodate flexible client server port
Diffstat (limited to 'src')
-rwxr-xr-xsrc/model_generation.py3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/model_generation.py b/src/model_generation.py
index 807b4f1..2c7a050 100755
--- a/src/model_generation.py
+++ b/src/model_generation.py
@@ -621,6 +621,7 @@ use ieee.numeric_std.all;
library work;
use work.Vhpi_Foreign.all;
use work.Utility_Package.all;
+use work.sock_pkg.all;
'''
@@ -690,7 +691,7 @@ map.append("\t\t\t);")
tb_clk= "clk_s <= not clk_s after 5 us;\n\n"
#Adding Process block for Vhpi
process_Vhpi=[]
-process_Vhpi.append("\tprocess\n\n\t\tbegin\n\n\t\tVhpi_Initialize;\n\t\twait until clk_s = '1';\n\t\twhile true loop\n\t\t\twait until clk_s = '0';\n\t\t\tVhpi_Listen;\n\t\t\twait for 1 us;\n\t\t\tVhpi_Send;\n\t\tend loop;\n\t\twait;\n\tend process;\n\n")
+process_Vhpi.append("\tprocess\n\t\tvariable sock_port : integer;\n\t\tbegin\n\t\tsock_port := sock_pkg_fun;\n\t\tVhpi_Initialize(sock_port);\n\t\twait until clk_s = '1';\n\t\twhile true loop\n\t\t\twait until clk_s = '0';\n\t\t\tVhpi_Listen;\n\t\t\twait for 1 us;\n\t\t\tVhpi_Send;\n\t\tend loop;\n\t\twait;\n\tend process;\n\n")
#Adding process block
process=[]
process.append("\tprocess\n\n")