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authorRahul Paknikar2019-06-25 09:40:43 +0530
committerGitHub2019-06-25 09:40:43 +0530
commit055431e4bee9a273bd5cff72b4f600033d0d09fb (patch)
tree9d4df3183f6f2004ebfba69013cdddc91b01c14a /src/model_generation.py
parentb86bc3c6f6121e0cbbc7fa1f47813047088a6ee3 (diff)
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-rw-r--r--src/model_generation.py7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/model_generation.py b/src/model_generation.py
index 15dc3e6..9a1aec8 100644
--- a/src/model_generation.py
+++ b/src/model_generation.py
@@ -92,7 +92,9 @@ data=read_file.readlines()
read_file.close()
#Extracting input and output port list from data
+print "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"
for line in data:
+ print line
if re.match(r'^\s*$', line):
pass
#print "Blank Line"
@@ -216,9 +218,9 @@ init_else='''
'''
els_evt_ptr=[]
-els_evt_count1=[]
+els_evt_count1=0
+els_evt_count2=0
for item in output_port:
- els_evt_count2=0
els_evt_ptr.append("_op_"+item.split(":")[0]+" = cm_event_get_ptr("+str(els_evt_count1)+","+str(els_evt_count2)+");")
els_evt_count2=els_evt_count2+1
els_evt_ptr.append("_op_"+item.split(":")[0]+"_old"+" = cm_event_get_ptr("+str(els_evt_count1)+","+str(els_evt_count2)+");")
@@ -612,6 +614,7 @@ ifspec.close()
print "Starting with testbench file"
testbench=open(fname.split('.')[0]+'_tb.vhdl','w')
+print fname.split('.')[0] + '_tb.vhdl'
#comment
comment_vhdl="--------------------------------------------------------------------------------\n--This testbench has been created by Ambikeshwar Srivastava, FOSSEE, IIT Bombay\n-------------------------------------------------------------------------------"
#Adding header, entity and architecture statement