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authorRahul P2019-11-19 12:32:39 +0530
committerGitHub2019-11-19 12:32:39 +0530
commita6c0b36fcaba6c1f2d366432b2386122674b4782 (patch)
tree18a02155e45110fd6419139e48f6d9b277ab9870 /Example/mux-demux/mux.vhdl
parent2fe70dd26008b0f4920928d592290614bf47ce5d (diff)
parent6e12269c0681dcfb0d1ec927670fb9d69464af9c (diff)
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Merge pull request #29 from rahulp13/master
Updated nghdl
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+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity mux is
+ port(A : in std_logic;
+ B : in std_logic;
+ C : in std_logic;
+ D : in std_logic;
+ S0 : in std_logic;
+ S1 : in std_logic;
+ Z: out std_logic);
+end mux;
+
+architecture bhv of mux is
+begin
+process (A,B,C,D,S0,S1) is
+begin
+ if (S0 ='0' and S1 = '0') then
+ Z <= A;
+ elsif (S0 ='0' and S1 = '1') then
+ Z <= B;
+ elsif (S0 ='1' and S1 = '0') then
+ Z <= C;
+ else
+ Z <= D;
+ end if;
+
+end process;
+end bhv;
+