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author | Rahul P | 2019-11-19 12:32:39 +0530 |
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committer | GitHub | 2019-11-19 12:32:39 +0530 |
commit | a6c0b36fcaba6c1f2d366432b2386122674b4782 (patch) | |
tree | 18a02155e45110fd6419139e48f6d9b277ab9870 /Example/logic_gates | |
parent | 2fe70dd26008b0f4920928d592290614bf47ce5d (diff) | |
parent | 6e12269c0681dcfb0d1ec927670fb9d69464af9c (diff) | |
download | nghdl-a6c0b36fcaba6c1f2d366432b2386122674b4782.tar.gz nghdl-a6c0b36fcaba6c1f2d366432b2386122674b4782.tar.bz2 nghdl-a6c0b36fcaba6c1f2d366432b2386122674b4782.zip |
Merge pull request #29 from rahulp13/master
Updated nghdl
Diffstat (limited to 'Example/logic_gates')
-rw-r--r-- | Example/logic_gates/inverter_gate.vhdl | 14 | ||||
-rw-r--r-- | Example/logic_gates/xor_gate.vhdl | 13 |
2 files changed, 27 insertions, 0 deletions
diff --git a/Example/logic_gates/inverter_gate.vhdl b/Example/logic_gates/inverter_gate.vhdl new file mode 100644 index 0000000..9825917 --- /dev/null +++ b/Example/logic_gates/inverter_gate.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity inverter_gate is + port ( i: in std_logic; + o: out std_logic); +end inverter_gate; + +architecture beh of inverter_gate is +begin + o <= not i; +end beh; + + diff --git a/Example/logic_gates/xor_gate.vhdl b/Example/logic_gates/xor_gate.vhdl new file mode 100644 index 0000000..da0da23 --- /dev/null +++ b/Example/logic_gates/xor_gate.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity xor_gate is + port (a : in std_logic; + b : in std_logic; + c : out std_logic); +end xor_gate; + +architecture rtl of xor_gate is + begin + c <= a xor b; +end rtl; |