Merge pull request #35 from saurabhb17/master

Changes for 1.1.3 version release

5 files changed, 95 insertions, 3 deletions

diff --git a/Example/logic_gates/and_gate.vhdl b/Example/logic_gates/and_gate.vhdl
new file mode 100644
index 0000000..689bcba
--- /dev/null
+++ b/Example/logic_gates/and_gate.vhdl
@@ -0,0 +1,33 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+
+entity and_gate is
+
+port(    a: in std_logic;
+         b: in std_logic;
+         c: out std_logic
+);
+
+end and_gate;
+
+architecture beh of and_gate is
+
+    begin
+
+    process(a, b)
+
+    begin
+
+    if (a='1' and b='1') then
+        c <= '1';
+
+    else 
+
+	c <= '0';
+
+    end if;
+
+    end process;
+
+end beh;
diff --git a/Example/logic_gates/inverter_gate.vhdl b/Example/logic_gates/inverter.vhdl
index 9825917..ee2d830 100644
--- a/Example/logic_gates/inverter_gate.vhdl
+++ b/Example/logic_gates/inverter.vhdl
@@ -1,12 +1,12 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-entity inverter_gate is
+entity inverter is
     port ( i: in std_logic;
            o: out std_logic);
-end inverter_gate;
+end inverter;
 
-architecture beh of inverter_gate is
+architecture beh of inverter is
 begin
     o <= not i;
 end beh;
diff --git a/Example/logic_gates/nand_gate.vhdl b/Example/logic_gates/nand_gate.vhdl
new file mode 100644
index 0000000..3736285
--- /dev/null
+++ b/Example/logic_gates/nand_gate.vhdl
@@ -0,0 +1,33 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+
+entity nand_gate is
+
+port(    a: in std_logic;
+         b: in std_logic;
+         c: out std_logic
+);
+
+end nand_gate;
+
+architecture beh of nand_gate is
+
+    begin
+
+    process(a, b)
+
+    begin
+
+    if (a='1' and b='1') then
+        c <= '0';
+
+    else 
+
+	c <= '1';
+
+    end if;
+
+    end process;
+
+end beh;
diff --git a/Example/logic_gates/nor_gate.vhdl b/Example/logic_gates/nor_gate.vhdl
new file mode 100644
index 0000000..0dcdab0
--- /dev/null
+++ b/Example/logic_gates/nor_gate.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity nor_gate is
+    port (a : in  std_logic;
+          b : in  std_logic;
+          c : out std_logic);
+end nor_gate;
+     
+architecture rtl of nor_gate is
+    begin
+		c <= a nor b;
+end rtl;
diff --git a/Example/logic_gates/or_gate.vhdl b/Example/logic_gates/or_gate.vhdl
new file mode 100644
index 0000000..d470c3d
--- /dev/null
+++ b/Example/logic_gates/or_gate.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity or_gate is
+    Port ( a : in  STD_LOGIC;    
+           b : in  STD_LOGIC;    
+           c : out  STD_LOGIC);    
+end or_gate;
+
+architecture behavioral of or_gate is
+begin
+c <= a or b;    
+end behavioral;