From eb95026ab9007631eb8e2a1c54dcd38fabcb60ad Mon Sep 17 00:00:00 2001
From: saurabhb17
Date: Wed, 18 Dec 2019 15:13:23 +0530
Subject: Examples Restructered

---
 Example/logic_gates/and_gate.vhdl      | 33 +++++++++++++++++++++++++++++++++
 Example/logic_gates/inverter.vhdl      | 14 ++++++++++++++
 Example/logic_gates/inverter_gate.vhdl | 14 --------------
 Example/logic_gates/nand_gate.vhdl     | 33 +++++++++++++++++++++++++++++++++
 Example/logic_gates/nor_gate.vhdl      | 13 +++++++++++++
 Example/logic_gates/or_gate.vhdl       | 13 +++++++++++++
 6 files changed, 106 insertions(+), 14 deletions(-)
 create mode 100644 Example/logic_gates/and_gate.vhdl
 create mode 100644 Example/logic_gates/inverter.vhdl
 delete mode 100644 Example/logic_gates/inverter_gate.vhdl
 create mode 100644 Example/logic_gates/nand_gate.vhdl
 create mode 100644 Example/logic_gates/nor_gate.vhdl
 create mode 100644 Example/logic_gates/or_gate.vhdl

(limited to 'Example/logic_gates')

diff --git a/Example/logic_gates/and_gate.vhdl b/Example/logic_gates/and_gate.vhdl
new file mode 100644
index 0000000..689bcba
--- /dev/null
+++ b/Example/logic_gates/and_gate.vhdl
@@ -0,0 +1,33 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+
+entity and_gate is
+
+port(    a: in std_logic;
+         b: in std_logic;
+         c: out std_logic
+);
+
+end and_gate;
+
+architecture beh of and_gate is
+
+    begin
+
+    process(a, b)
+
+    begin
+
+    if (a='1' and b='1') then
+        c <= '1';
+
+    else 
+
+	c <= '0';
+
+    end if;
+
+    end process;
+
+end beh;
diff --git a/Example/logic_gates/inverter.vhdl b/Example/logic_gates/inverter.vhdl
new file mode 100644
index 0000000..ee2d830
--- /dev/null
+++ b/Example/logic_gates/inverter.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity inverter is
+    port ( i: in std_logic;
+           o: out std_logic);
+end inverter;
+
+architecture beh of inverter is
+begin
+    o <= not i;
+end beh;
+
+
diff --git a/Example/logic_gates/inverter_gate.vhdl b/Example/logic_gates/inverter_gate.vhdl
deleted file mode 100644
index 9825917..0000000
--- a/Example/logic_gates/inverter_gate.vhdl
+++ /dev/null
@@ -1,14 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity inverter_gate is
-    port ( i: in std_logic;
-           o: out std_logic);
-end inverter_gate;
-
-architecture beh of inverter_gate is
-begin
-    o <= not i;
-end beh;
-
-
diff --git a/Example/logic_gates/nand_gate.vhdl b/Example/logic_gates/nand_gate.vhdl
new file mode 100644
index 0000000..3736285
--- /dev/null
+++ b/Example/logic_gates/nand_gate.vhdl
@@ -0,0 +1,33 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+
+entity nand_gate is
+
+port(    a: in std_logic;
+         b: in std_logic;
+         c: out std_logic
+);
+
+end nand_gate;
+
+architecture beh of nand_gate is
+
+    begin
+
+    process(a, b)
+
+    begin
+
+    if (a='1' and b='1') then
+        c <= '0';
+
+    else 
+
+	c <= '1';
+
+    end if;
+
+    end process;
+
+end beh;
diff --git a/Example/logic_gates/nor_gate.vhdl b/Example/logic_gates/nor_gate.vhdl
new file mode 100644
index 0000000..0dcdab0
--- /dev/null
+++ b/Example/logic_gates/nor_gate.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity nor_gate is
+    port (a : in  std_logic;
+          b : in  std_logic;
+          c : out std_logic);
+end nor_gate;
+     
+architecture rtl of nor_gate is
+    begin
+		c <= a nor b;
+end rtl;
diff --git a/Example/logic_gates/or_gate.vhdl b/Example/logic_gates/or_gate.vhdl
new file mode 100644
index 0000000..d470c3d
--- /dev/null
+++ b/Example/logic_gates/or_gate.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity or_gate is
+    Port ( a : in  STD_LOGIC;    
+           b : in  STD_LOGIC;    
+           c : out  STD_LOGIC);    
+end or_gate;
+
+architecture behavioral of or_gate is
+begin
+c <= a or b;    
+end behavioral;
-- 
cgit