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author | saurabhb17 | 2019-12-30 12:37:57 +0530 |
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committer | GitHub | 2019-12-30 12:37:57 +0530 |
commit | 9faa3ee18b0fe7ec50399b06280a5247658c3e9c (patch) | |
tree | 0ff4c4791a65364e3b93c91f56342569c7f7a7c9 /Example/logic_gates/nor_gate.vhdl | |
parent | 04d9c666b4bb19936dfa469f536fb38107e631eb (diff) | |
parent | fc1fb5abffa152808c621be38c8fbbe8de769b19 (diff) | |
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Merge pull request #35 from saurabhb17/master
Changes for 1.1.3 version release
Diffstat (limited to 'Example/logic_gates/nor_gate.vhdl')
-rw-r--r-- | Example/logic_gates/nor_gate.vhdl | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/Example/logic_gates/nor_gate.vhdl b/Example/logic_gates/nor_gate.vhdl new file mode 100644 index 0000000..0dcdab0 --- /dev/null +++ b/Example/logic_gates/nor_gate.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity nor_gate is + port (a : in std_logic; + b : in std_logic; + c : out std_logic); +end nor_gate; + +architecture rtl of nor_gate is + begin + c <= a nor b; +end rtl; |