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authorRahul Paknikar2019-06-25 09:51:28 +0530
committerGitHub2019-06-25 09:51:28 +0530
commit26543fb77ba71c77292547f64b24d1fb0658ec72 (patch)
treef4b8e6db228d5644bb0f1342638ce012fa74f519 /Example/full_adder
parentaa538a95b5ff747ad9fa3455ac2a6c88dcb0becb (diff)
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Delete trial_ha.vhdl
Diffstat (limited to 'Example/full_adder')
-rw-r--r--Example/full_adder/trial_ha.vhdl17
1 files changed, 0 insertions, 17 deletions
diff --git a/Example/full_adder/trial_ha.vhdl b/Example/full_adder/trial_ha.vhdl
deleted file mode 100644
index 30e7938..0000000
--- a/Example/full_adder/trial_ha.vhdl
+++ /dev/null
@@ -1,17 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity trial_ha is
- port (
- i_bit : in std_logic_vector(1 downto 0);
- o_sum : out std_logic_vector(0 downto 0);
- o_carry : out std_logic_vector(0 downto 0)
- );
-end trial_ha;
-
-architecture rtl of trial_ha is
-begin
- o_sum <= i_bit(0) xor i_bit(1);
- o_carry <= i_bit(0) and i_bit(1);
-end rtl; \ No newline at end of file