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| author | saurabhb17 | 2019-12-30 12:33:07 +0530 |
|---|---|---|
| committer | saurabhb17 | 2019-12-30 12:33:07 +0530 |
| commit | 09181d02231704f6d691eccfa380eea77503383d (patch) | |
| tree | c74e4fefc7a8363051afcdc62c5e5792f9ccd253 /Example/combinational_logic/full_adder/full_adder_sl.vhdl | |
| parent | 9d6371199374495c036588f269e55857939fe2ca (diff) | |
| download | nghdl-09181d02231704f6d691eccfa380eea77503383d.tar.gz nghdl-09181d02231704f6d691eccfa380eea77503383d.tar.bz2 nghdl-09181d02231704f6d691eccfa380eea77503383d.zip | |
Examples modified
Diffstat (limited to 'Example/combinational_logic/full_adder/full_adder_sl.vhdl')
| -rw-r--r-- | Example/combinational_logic/full_adder/full_adder_sl.vhdl | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/Example/combinational_logic/full_adder/full_adder_sl.vhdl b/Example/combinational_logic/full_adder/full_adder_sl.vhdl index e830563..99976ba 100644 --- a/Example/combinational_logic/full_adder/full_adder_sl.vhdl +++ b/Example/combinational_logic/full_adder/full_adder_sl.vhdl @@ -1,3 +1,4 @@ +-- This file uses only std_logic(sl) variable types library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; @@ -16,4 +17,4 @@ architecture rtl of full_adder_sl is begin o_sum <= i_bit1 xor i_bit2 xor i_bit3; o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1); -end rtl;
\ No newline at end of file +end rtl; |