Examples Restructered

2 files changed, 62 insertions, 0 deletions

diff --git a/Example/combinational_logic/counter/counter.vhdl b/Example/combinational_logic/counter/counter.vhdl
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+++ b/Example/combinational_logic/counter/counter.vhdl
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+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity counter is
+port(C : in std_logic;
+     CLR : in std_logic;
+     Q : out std_logic_vector(3 downto 0));
+end counter;
+
+architecture bhv of counter is
+
+	signal tmp: std_logic_vector(3 downto 0);
+	begin
+	process (C, CLR)
+
+		begin
+			if (CLR='1') then
+			tmp <= "0000";
+
+			elsif (C'event and C='1') then
+			tmp <= std_logic_vector(to_unsigned(1+to_integer(unsigned(tmp)), tmp'length));
+
+			end if;
+
+	end process;
+	Q <= tmp;
+
+end bhv;
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diff --git a/Example/combinational_logic/counter/updown_counter.vhdl b/Example/combinational_logic/counter/updown_counter.vhdl
new file mode 100644
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+++ b/Example/combinational_logic/counter/updown_counter.vhdl
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+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+
+entity updown_counter is
+    Port ( clk: in std_logic;
+           reset: in std_logic;
+     up_down: in std_logic;
+           counter: out std_logic_vector(3 downto 0)
+     );
+end updown_counter;
+
+architecture Behavioral of updown_counter is
+signal tmp: std_logic_vector(3 downto 0);
+begin
+
+process(clk,reset)
+begin
+    if(reset='1') then
+         tmp <= "0000";
+    elsif(clk'event and clk='1') then
+         if(up_down='1') then
+           tmp <= std_logic_vector(to_unsigned(to_integer(unsigned(tmp)-1), tmp'length));
+         else 
+           tmp <= std_logic_vector(to_unsigned(to_integer(unsigned(tmp)+1), tmp'length));
+         end if;
+    end if;
+end process;
+ counter <= std_logic_vector(tmp);
+
+end Behavioral;
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