Update and rename trial_fa.vhdl to full_adder.vhdl

1 files changed, 4 insertions, 4 deletions

diff --git a/Example/full_adder/trial_fa.vhdl b/Example/full_adder/full_adder.vhdl
index 6357aa2..745fac3 100644
--- a/Example/full_adder/trial_fa.vhdl
+++ b/Example/full_adder/full_adder.vhdl
@@ -2,7 +2,7 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
  
-entity trial_fa is
+entity full_adder is
   port (
     i_bit1  : in std_logic_vector(0 downto 0);
     i_bit2  : in std_logic_vector(0 downto 0);
@@ -10,10 +10,10 @@ entity trial_fa is
     o_sum   : out std_logic_vector(0 downto 0);
     o_carry : out std_logic_vector(0 downto 0)
     );
-end trial_fa;
+end full_adder;
  
-architecture rtl of trial_fa is
+architecture rtl of full_adder is
 begin
   o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
   o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
-end rtl;
\ No newline at end of file
+end rtl;