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| author | rahulp13 | 2022-02-20 22:24:55 +0530 |
|---|---|---|
| committer | rahulp13 | 2022-02-20 23:00:46 +0530 |
| commit | 42dd8bcc1294303cdbfc802e7e5be68ef38ca912 (patch) | |
| tree | f2b6f0b2aac1c706fc83893ea636ad39c04d598d | |
| parent | b00d3b9f00a16995f7aa4c51bd500b0c3d5ed425 (diff) | |
| download | nghdl-42dd8bcc1294303cdbfc802e7e5be68ef38ca912.tar.gz nghdl-42dd8bcc1294303cdbfc802e7e5be68ef38ca912.tar.bz2 nghdl-42dd8bcc1294303cdbfc802e7e5be68ef38ca912.zip | |
added description for verilog support
| -rw-r--r-- | README.md | 7 |
1 files changed, 4 insertions, 3 deletions
@@ -32,13 +32,14 @@ GHDL's foreign language interface is used for this inter-process communication. ## Features -* Support for 500 digital models. -* Support for digital models upto 64 output ports/pins. -* Multiple instances of same digital model. +* Support for nearly 500 VHDL digital models. +* Support for VHDL digital models upto 64 output ports/pins. +* Support for Verilog digital models. ## Pre-requisites * [GHDL (LLVM - v0.37)](http://ghdl.free.fr/) +* [Verilator (v4.210)](https://www.veripool.org/verilator/) * [Ngspice (v35+)](http://ngspice.sourceforge.net/) |