Merge pull request #34 from rahulp13/master

up counter example

3 files changed, 39 insertions, 43 deletions

diff --git a/Example/counter/up_counter.vhdl b/Example/counter/up_counter.vhdl
new file mode 100644
index 0000000..bd27fcf
--- /dev/null
+++ b/Example/counter/up_counter.vhdl
@@ -0,0 +1,34 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+       
+entity up_counter is
+	port(Clock : in  std_logic;
+    	CLR : in  std_logic;
+        	Q : out std_logic_vector(3 downto 0));        
+end up_counter;
+       
+architecture beh of up_counter is
+	signal tmp: unsigned(3 downto 0) := "0000";
+                
+    --------------- Other ways to initialize --------------
+    -- signal tmp: unsigned(3 downto 0) := x"0";
+    -- signal tmp: unsigned(3 downto 0) := (others => '0');
+    -------------------------------------------------------
+
+    begin
+    process (Clock, CLR)        
+        begin          
+            if (CLR='1') then          
+                tmp <= "0000";          
+            elsif (Clock'event and Clock='1') then  
+                if tmp="1111" then
+                	tmp <= x"0";
+                else      
+                	tmp <= tmp +1;        
+                end if;  
+            end if;          
+    end process;
+           
+    Q <= std_logic_vector (tmp);   
+end beh;
\ No newline at end of file
diff --git a/Example/counter/counter.vhdl b/Example/counter/up_counter_slv.vhdl
index ba14df8..afef463 100644
--- a/Example/counter/counter.vhdl
+++ b/Example/counter/up_counter_slv.vhdl
@@ -1,29 +1,23 @@
 library ieee;
-
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-entity counter is
+entity up_counter_slv is
 port(C : in std_logic;
      CLR : in std_logic;
      Q : out std_logic_vector(3 downto 0));
-end counter;
-
-architecture bhv of counter is
+end up_counter_slv;
 
+architecture bhv of up_counter_slv is
 	signal tmp: std_logic_vector(3 downto 0);
 	begin
 	process (C, CLR)
-
 		begin
 			if (CLR='1') then
-			tmp <= "0000";
-
+				tmp <= "0000";
 			elsif (C'event and C='1') then
-			tmp <= std_logic_vector(to_unsigned(1+to_integer(unsigned(tmp)), tmp'length));
-
+				tmp <= std_logic_vector(to_unsigned(1+to_integer(unsigned(tmp)), tmp'length));
 			end if;
-
 	end process;
 	Q <= tmp;
 
diff --git a/Example/counter/updown_counter.vhdl b/Example/counter/updown_counter.vhdl
deleted file mode 100644
index 922ee67..0000000
--- a/Example/counter/updown_counter.vhdl
+++ /dev/null
@@ -1,32 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-
-entity updown_counter is
-    Port ( clk: in std_logic;
-           reset: in std_logic;
-     up_down: in std_logic;
-           counter: out std_logic_vector(3 downto 0)
-     );
-end updown_counter;
-
-architecture Behavioral of updown_counter is
-signal tmp: std_logic_vector(3 downto 0);
-begin
-
-process(clk,reset)
-begin
-    if(reset='1') then
-         tmp <= "0000";
-    elsif(clk'event and clk='1') then
-         if(up_down='1') then
-           tmp <= std_logic_vector(to_unsigned(to_integer(unsigned(tmp)-1), tmp'length));
-         else 
-           tmp <= std_logic_vector(to_unsigned(to_integer(unsigned(tmp)+1), tmp'length));
-         end if;
-    end if;
-end process;
- counter <= std_logic_vector(tmp);
-
-end Behavioral;
\ No newline at end of file