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[size] 1400 967
[pos] -1 -1
*-16.314999 5250420000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] u2_sim_top.
[treeopen] u2_sim_top.u2_basic.
[treeopen] u2_sim_top.u2_basic.MAC_top.
[treeopen] u2_sim_top.u2_basic.MAC_top.U_MAC_tx.
@22
u2_sim_top.GMII_TXD[7:0]
@28
u2_sim_top.GMII_TX_EN
@200
-
@24
u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.fc_hwmark[15:0]
u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.fc_lwmark[15:0]
@28
u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.pause_frame_send_en
@22
u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.pause_quanta_set[15:0]
@28
u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rst
u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rx_clk
@24
u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rx_fifo_space[15:0]
@28
u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.tx_clk
@200
-
@28
u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_gen
u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_gen_complete
u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_int
u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_int_d1
@200
-
@28
u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_gen
u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_gen_complete
u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_int
u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_int_d1
@200
-
@28
u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_apply
@22
u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta[15:0]
u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_counter[15:0]
@28
u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_sub
u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_val
u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pqval_d1
u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pqval_d2
u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.rst
u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.tx_clk
u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.tx_pause_en
u2_sim_top.u2_basic.proc_int
@22
u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.countdown[21:0]
u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_counter[15:0]
@25
u2_sim_top.u2_basic.MAC_top.U_MAC_tx.U_MAC_tx_ctrl.Current_state[3:0]
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