usrp2/fpga/eth/bench/verilog/xlnx_glbl.v


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module xlnx_glbl
(
  GSR,
  GTS
);

  //--------------------------------------------------------------------------
  // Parameters
  //--------------------------------------------------------------------------

  //--------------------------------------------------------------------------
  // IO declarations
  //--------------------------------------------------------------------------

  output GSR;
  output GTS;

  //--------------------------------------------------------------------------
  // Local declarations
  //--------------------------------------------------------------------------

  //--------------------------------------------------------------------------
  // Internal declarations
  //--------------------------------------------------------------------------

  assign GSR = 0;
  assign GTS = 0;
  
endmodule