1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
|
// Note -- clocks must be synchronous (derived from the same source)
// Assumes alt_clk is running at a multiple of wb_clk
module wb_readback_mux
(input wb_clk_i,
input wb_rst_i,
input wb_stb_i,
input [15:0] wb_adr_i,
output reg [31:0] wb_dat_o,
output reg wb_ack_o,
input [31:0] word00,
input [31:0] word01,
input [31:0] word02,
input [31:0] word03,
input [31:0] word04,
input [31:0] word05,
input [31:0] word06,
input [31:0] word07,
input [31:0] word08,
input [31:0] word09,
input [31:0] word10,
input [31:0] word11,
input [31:0] word12,
input [31:0] word13,
input [31:0] word14,
input [31:0] word15
);
always @(posedge wb_clk_i)
if(wb_rst_i)
wb_ack_o <= 0;
else
wb_ack_o <= wb_stb_i & ~wb_ack_o;
always @(posedge wb_clk_i)
case(wb_adr_i[5:2])
0 : wb_dat_o <= word00;
1 : wb_dat_o <= word01;
2 : wb_dat_o <= word02;
3 : wb_dat_o <= word03;
4 : wb_dat_o <= word04;
5 : wb_dat_o <= word05;
6 : wb_dat_o <= word06;
7 : wb_dat_o <= word07;
8 : wb_dat_o <= word08;
9 : wb_dat_o <= word09;
10: wb_dat_o <= word10;
11: wb_dat_o <= word11;
12: wb_dat_o <= word12;
13: wb_dat_o <= word13;
14: wb_dat_o <= word14;
15: wb_dat_o <= word15;
endcase // case(addr_reg[3:0])
endmodule // wb_readback_mux
|
