usrp2/fpga/control_lib/clock_control_tb.v


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35


module clock_control_tb();
   
  clock_control clock_control
    (.reset(reset),
     .aux_clk(aux_clk),  
     .clk_fpga(clk_fpga),
     .clk_en(clk_en),    
     .clk_sel(clk_sel),  
     .clk_func(clk_func), 
     .clk_status(clk_status),
     
     .sen(sen),   
     .sclk(sclk), 
     .sdi(sdi),
     .sdo(sdo)
     );

   reg reset, aux_clk;
   
   wire [1:0] clk_sel, clk_en;
   
   initial reset = 1'b1;
   initial #1000 reset = 1'b0;
   
   initial aux_clk = 1'b0;
   always #10 aux_clk = ~aux_clk;
   
   initial $dumpfile("clock_control_tb.vcd");
   initial $dumpvars(0,clock_control_tb);
   
   initial #10000 $finish;
   
endmodule // clock_control_tb