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path: root/usrp2/fpga/control_lib/clock_control_tb.sav
blob: be4001dc5bb16c41ddd23466a283769942237871 (plain)
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[size] 1400 971
[pos] -1 -1
*-7.848898 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
@28
clock_control_tb.aux_clk
clock_control_tb.reset
clock_control_tb.sclk
clock_control_tb.sdi
clock_control_tb.sdo
clock_control_tb.sen
@22
clock_control_tb.clock_control.counter[7:0]
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clock_control_tb.clock_control.done
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clock_control_tb.clock_control.entry[5:0]
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clock_control_tb.clock_control.read
clock_control_tb.clock_control.reset
clock_control_tb.clock_control.sclk
clock_control_tb.clock_control.w[1:0]
clock_control_tb.sen
clock_control_tb.sdo
clock_control_tb.sclk
clock_control_tb.clock_control.done
clock_control_tb.clock_control.start
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clock_control_tb.clock_control.addr_data[20:0]