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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/
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	(text "inst" (rect 8 168 25 180)(font "Arial" ))
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		(input)
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	)
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		(input)
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	)
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		(text "wrfull" (rect 113 34 138 47)(font "Arial" (font_size 8)))
		(line (pt 160 40)(pt 144 40)(line_width 1))
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		(output)
		(text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
		(text "q[15..0]" (rect 105 90 141 103)(font "Arial" (font_size 8)))
		(line (pt 160 96)(pt 144 96)(line_width 3))
	)
	(port
		(pt 160 120)
		(output)
		(text "rdempty" (rect 0 0 46 14)(font "Arial" (font_size 8)))
		(text "rdempty" (rect 102 114 140 127)(font "Arial" (font_size 8)))
		(line (pt 160 120)(pt 144 120)(line_width 1))
	)
	(port
		(pt 160 136)
		(output)
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		(text "rdusedw[11..0]" (rect 67 130 135 143)(font "Arial" (font_size 8)))
		(line (pt 160 136)(pt 144 136)(line_width 3))
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	(drawing
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)