usrp/fpga/inband_lib/usb_fifo_reader.v


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

module usb_fifo_reader (
      input usbclk,
      input bus_reset, 
      input RD,
      output rdreq,
      );
      
    // FX2 Bug Fix
    reg [8:0] read_count;
    always @(negedge usbclk)
        if(bus_reset)
            read_count <= #1 9'd0;
        else if(RD & ~read_count[8])
            read_count <= #1 read_count + 9'd1;
        else
            read_count <= #1 RD ? read_count : 9'b0;
            
    assign rdreq = RD & ~read_count[8];
    
    
 
endmodule